 Adrian Conlon
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072a8dd984
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Blargg tests run again. Corrected speed issue of MemoryMappings being created too often and bus data being trashed by a write to ROM.
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2026-05-17 09:50:12 +01:00 |
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Adrian Conlon
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9a011b3c57
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Start implementing HD6309. Introduction of 32-bit operations has forced me to rename some of "Word" methods to better indicate size
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2026-05-16 21:10:23 +01:00 |
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Adrian Conlon
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ac200d7f76
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Simplify ignored return value handling
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2026-05-12 22:21:13 +01:00 |
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Adrian Conlon
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69a0865ee9
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Start work towards WDC 65C02 implementation
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2026-05-02 17:02:36 +01:00 |
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Adrian Conlon
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de12029c13
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Speedup Z80 by encouraging runtime inlining of code
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2026-04-20 18:56:05 +01:00 |
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Adrian Conlon
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699791f7a4
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Simplify intermediate 16-bit register usage
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2026-04-16 13:47:24 +01:00 |
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Adrian Conlon
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53e33b9eef
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Some simplifications
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2026-04-07 12:02:31 +01:00 |
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Adrian Conlon
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98448b0524
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Small consistency changes for LR35902 core
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2026-03-21 12:44:19 +00:00 |
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Adrian Conlon
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a8ef9aa7db
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simplification and unification of build stuff
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2026-02-16 11:15:58 +00:00 |
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Adrian Conlon
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e1bf58afbc
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More sharing of concepts between all Intel style processors
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2026-01-03 23:17:30 +00:00 |
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Adrian Conlon
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1dfd9621a1
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Share some more common code between Intel style procesors
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2025-10-15 19:46:10 +01:00 |
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Adrian Conlon
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ceacac4741
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Fix up some oddities in the EightBit library
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2025-10-06 13:44:31 +01:00 |
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Adrian Conlon
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1779d1dc40
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Intel processors all seem to act slightly differently with regards to HALT
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2025-08-17 12:03:51 +01:00 |
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Adrian Conlon
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c67e376d4f
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Add support for checking deferred EI correctness
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2025-08-14 14:57:51 +01:00 |
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Adrian Conlon
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4da07a8fa2
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Correct interrupt flag checks in Gameboy checker
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2025-08-14 11:18:02 +01:00 |
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Adrian Conlon
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7951abde00
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Add support for "Gameboy Doctor" log checker.
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2025-08-13 14:01:14 +01:00 |
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Adrian Conlon
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25ca534186
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The EI instructions is actually a deferred instruction
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2025-08-10 21:47:15 +01:00 |
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Adrian Conlon
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558da38f12
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Note commonality between Intel-style processors
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2025-08-10 12:43:34 +01:00 |
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Adrian Conlon
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14e4132d34
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Small consistency change
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2025-08-06 16:54:14 +01:00 |
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Adrian Conlon
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9d208de9bb
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Explicitly state order of operations in code, rather than relying upon RAII etc. (for speed. Much faster)
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2025-08-04 15:47:26 +01:00 |
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Adrian Conlon
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6143a9d285
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Hack to allow single step tests to completely work: disable IO area triggers.
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2025-08-01 22:59:00 +01:00 |
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Adrian Conlon
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60ef099208
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Tidy some inconsistencies in various emulation
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2025-08-01 15:01:20 +01:00 |
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Adrian Conlon
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2f338c6c46
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Tidy register increment/decrement a little.
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2025-07-25 16:32:30 +01:00 |
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 Adrian Conlon
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36e983526e
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Add increment/decrement operations to the Register16 class
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2025-05-11 19:24:40 +01:00 |
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Adrian Conlon
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e1696721f6
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Simplifications and refactorings in th intel processors
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2025-05-05 21:06:39 +01:00 |
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Adrian Conlon
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93e09c192f
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Share instruction fetch and halt implementations
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2025-05-04 11:41:28 +01:00 |
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Adrian Conlon
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2336222c97
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Push more core processor handling into base classes.
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2025-05-04 10:53:23 +01:00 |
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Adrian Conlon
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47374e591d
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With my correct implementation of HALT, I need the fetch to take place during a halted state
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2025-05-04 08:56:22 +01:00 |
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Adrian Conlon
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cbe871d365
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Isolate program counter increment/decrement (to be used for HALT processing)
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2025-05-03 23:25:06 +01:00 |
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Adrian Conlon
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080f203a55
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Unify Intel style JR CC code and fix SM83 timing issues.
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2025-05-03 12:09:34 +01:00 |
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Adrian Conlon
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0679b95b77
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Correct LR35902 HALT test. Whatever problems this has, won't be solved by a hack
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2025-05-03 11:58:57 +01:00 |
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Adrian Conlon
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e1aa220409
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Further Z80 timing fixes: 290 failures
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2025-05-03 00:09:19 +01:00 |
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Adrian Conlon
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dd1d141f15
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Simplify conditional flag handling in intel processors
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2025-04-29 12:27:39 +01:00 |
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Adrian Conlon
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973590690c
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Fix a bunch of analysis issues
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2025-04-01 09:32:29 +01:00 |
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Adrian Conlon
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b461eb97d6
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Prefer to use events directly, rather than through "On" methods
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2025-03-29 11:31:47 +00:00 |
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Adrian Conlon
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87abbaa75e
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Tidy IO page access
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2025-03-28 14:50:53 +00:00 |
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Adrian Conlon
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fa48a64cac
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Take advantage of some simplifications
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2025-03-28 09:17:09 +00:00 |
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Adrian Conlon
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3a9e89f009
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Tidy a couple of IO effects in the LR35902 core
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2025-03-28 09:03:32 +00:00 |
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Adrian Conlon
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4d0059ad94
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Only 7 failing instructions now
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2025-03-27 14:34:54 +00:00 |
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Adrian Conlon
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4db203de48
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All interrupt handling state tests to work
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2025-03-27 11:13:41 +00:00 |
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Adrian Conlon
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3ca3d60caf
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Correct some timing issues in GB core
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2025-03-27 10:19:18 +00:00 |
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Adrian Conlon
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08089823c2
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First stab at getting LR35902 HarteTests running. Not bad, so far!
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2025-03-26 21:16:37 +00:00 |
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Adrian Conlon
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f31442511f
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LR35902 analysis suggestions
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2025-01-26 21:17:07 +00:00 |
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Adrian Conlon
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4b4181e12d
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Synchonise with unmanaged GB implementation
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2024-10-14 11:04:51 +01:00 |
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Adrian Conlon
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fa13852e53
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Sort out GB timing (enough to pass Blargg, anyway)
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2024-10-12 14:38:45 +01:00 |
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Adrian Conlon
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0bc3cb9d03
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first round of .net 9 analysis
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2024-10-12 13:15:14 +01:00 |
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Adrian Conlon
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b38462bddf
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.net 9 gb analysis changes
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2024-10-12 12:57:38 +01:00 |
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Adrian Conlon
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3d9b0aac56
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Update to .Net 9
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2024-10-12 08:49:47 +01:00 |
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Adrian Conlon
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90c887d169
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Use intrinsics, if possible
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2024-08-05 20:32:34 +01:00 |
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Adrian Conlon
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c8ac0f20dc
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Step can be split a little to make it easier to override.
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2024-07-24 17:21:49 +01:00 |
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