Adrian Conlon
e0235f396e
IDE suggestions
2024-05-19 09:07:20 +01:00
Adrian Conlon
47ecdad3e8
Work towards accurate bus/memory/io timings. Especially Z80 m-cycle timing.
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Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
2020-07-05 00:09:51 +01:00
Adrian Conlon
cd4af67177
Work my way through a bunch of the analysis suggestions.
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Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
2020-06-22 00:00:15 +01:00
Adrian Conlon
aca81384c3
Correct PC power on value issue.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-09-07 11:16:03 +01:00
Adrian Conlon
f01e3e0430
Tighten up the sequence associated with changing pin levels + fix persistent HALT/PC bug
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-09-06 22:50:21 +01:00
Adrian Conlon
bc491884b0
Synchronise HALT implementation for Intel style processors with the C++ version.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-08-29 09:05:31 +01:00
Adrian Conlon
84284d62b5
Fuse fixes: Correct JR cc from unnecessary extra read of offset.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-08-15 14:30:12 +01:00
Adrian Conlon
1d976e811d
Introduce a little consistency with regards to pin naming and usage.
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Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
2019-04-23 00:58:33 +01:00
Adrian Conlon
e80963260d
Try to avoid copying around Register16 references, if possible.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-03-07 01:21:00 +00:00
Adrian Conlon
03caba99dc
Follow most of the guideline suggestions from VS2019 preview. Pretty good suggestions!
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-22 22:33:51 +00:00
Adrian Conlon
28b7a88f0f
Use the correct virtual methods: BusRead and BusWrite to control bus access for Z80 a la M6502 implementation.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-22 19:59:42 +00:00
Adrian Conlon
27e1c5c9f8
Make Register16 a class, rather than struct. Tricky, but a bit faster than before.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-21 19:58:49 +00:00
Adrian Conlon
a144cf19a1
Whoops: missed bus read/write clock ticks in the 6502 emulator.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-18 00:52:45 +00:00
Adrian Conlon
ea82c58777
Add Z80 processor (untested, but complete)
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-16 21:32:34 +00:00
Adrian Conlon
c6a7003b8d
Help out callers using Register16 arguments a little: Don't always require the ".Word" property to be passed.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-15 00:26:01 +00:00
Adrian Conlon
63db46a7bc
Resurrect the Register16 class. This (or something *very* much like it) is going to be necessary to add a Z80 emulator (reference access to the high/low parts of 16-bit registers).
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-14 23:01:31 +00:00
Adrian Conlon
0e8a530573
More analysis suggested tidy ups.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-06 23:41:56 +00:00
Adrian Conlon
224000c4c7
Not sure if this was a really good idea, but integrated StyleCop rules into the builds. Corrected all except documentation problems.
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-04 23:52:21 +00:00
Adrian Conlon
d4a35c402c
A few small consistency updates:
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1) Drop Get/SetPagedByte in favour of normal BusRead/Write
2) Tidy some "using" statements
3) More "expression body" usage, if possible
4) Use field initialisation, rather than construction, if possible
5) Correct IntelProcessor register set/get methods (there were remnants of "copy pasta" code)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-03 20:29:52 +00:00
Adrian Conlon
3c5e292eae
Drop Register16 support (replaced with explicit ushort), add some unit tests (Chip class only at present)
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Now runs some instructions before going wrong...
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-03 00:42:55 +00:00
Adrian Conlon
9a06b1743f
Port of EightBit library to .Net (unworking!)
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Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
2019-02-02 15:12:51 +00:00
