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898a2bc7ea79dc098e2784b448f889def2de9343
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100 Commits

Author SHA1 Message Date
Adrian Conlon
898a2bc7ea Try to bring the Z80 fusetest back to life 2025-05-03 02:09:31 +01:00
Adrian Conlon
946121defb Fix HALT instruction 2025-05-03 02:08:52 +01:00
Adrian Conlon
561483d65d More timing fixes. 255 timing errors 2025-05-03 01:31:44 +01:00
Adrian Conlon
f4f4357a3e More z80 timing fixes, 261 errors 2025-05-03 00:51:20 +01:00
Adrian Conlon
e1aa220409 Further Z80 timing fixes: 290 failures 2025-05-03 00:09:19 +01:00
Adrian Conlon
175069d6bf More Z80 timing fixes 2025-05-02 20:18:04 +01:00
Adrian Conlon
3617608e8c Fix a number of write timing issues 2025-05-02 17:46:33 +01:00
Adrian Conlon
fda52af260 Only DJNZ has the extra tick (presumably to decrement the B register) 2025-05-02 14:07:15 +01:00
Adrian Conlon
935466ad6f Correct timing issues both conditional and unconditional relative jumpson Z80 2025-05-02 14:03:15 +01:00
Adrian Conlon
9670c3fd21 Start correcting timing issues in my Z80 implementation 2025-05-02 12:11:54 +01:00
Adrian Conlon
5bae07ff8d Add single stepping Z80 testing code 2025-05-02 10:50:49 +01:00
Adrian Conlon
dd1d141f15 Simplify conditional flag handling in intel processors 2025-04-29 12:27:39 +01:00
Adrian Conlon
1b1b92ac2c More event handling simplification 2025-03-29 13:18:54 +00:00
Adrian Conlon
3d6b549c76 Turns out using lambdas to control pins is lovely and correct, but terribly slow. Back to a more traditional method. 2025-03-24 20:18:04 +00:00
Adrian Conlon
d4dc99b454 Use lambda functions to simplify CPU pin control 2025-03-23 11:08:36 +00:00
Adrian Conlon
a9db2f58bd miscellaneous fixes, especiall flags 2025-03-18 18:38:47 +00:00
Adrian Conlon
e8d770c6bb Simplify i/o port handling in Z80 implementation 2025-01-27 21:23:47 +00:00
Adrian Conlon
1b8925ebe4 Remove extra blank line 2024-10-14 11:24:09 +01:00
Adrian Conlon
4839f3fc04 .net 9 analysis 2024-10-12 12:26:21 +01:00
Adrian Conlon
f6829f2ec0 Z80 .net 9 analysis changes 2024-10-12 12:09:22 +01:00
Adrian Conlon
3b80ee7b37 Shared test harness 2024-10-12 11:48:54 +01:00
Adrian Conlon
3d9b0aac56 Update to .Net 9 2024-10-12 08:49:47 +01:00
Adrian Conlon
5c71acc40a More analysis code changes 2024-10-10 00:11:55 +01:00
Adrian Conlon
3cbc7f32d2 More analysis fixes 2024-10-09 22:46:25 +01:00
Adrian Conlon
647be6f224 More style changes 2024-10-09 21:16:55 +01:00
Adrian Conlon
d67cafe297 Prefer a more straightforward register exchange 2024-09-27 12:43:14 +01:00
Adrian Conlon
e764033948 Make the Z80 test harness more like the 6502 2024-09-27 12:41:06 +01:00
Adrian Conlon
c8ac0f20dc Step can be split a little to make it easier to override. 2024-07-24 17:21:49 +01:00
Adrian Conlon
ee584867c2 Modernise some more c# code 2024-07-18 11:38:02 +01:00
Adrian Conlon
d80f340081 Simplfy access to Z80 registers 2024-07-04 08:47:53 +01:00
Adrian Conlon
0c8ed57b0d Add easy to use Register16 assignment methods 2024-07-01 23:27:35 +01:00
Adrian Conlon
38c4c2972c More Word optimisations 2024-06-30 16:04:15 +01:00
Adrian Conlon
0039b06465 Couple of hacked Z80 disassembler changes 2024-06-30 15:06:46 +01:00
Adrian Conlon
1a9b6d3db6 More "Word" optimisations 2024-06-30 14:36:32 +01:00
Adrian Conlon
d8fad7b988 Try to minimise use of "Word" from Register16 2024-06-30 12:30:07 +01:00
Adrian Conlon
9979606757 Small performance/readability mod 2024-06-29 18:36:54 +01:00
Adrian Conlon
6e46c8e47f Rationalise use of "intermediate" Register16 2024-06-29 13:38:55 +01:00
Adrian Conlon
a64f370d7c Compilation fixes 2024-05-29 10:56:16 +01:00
Adrian Conlon
e0235f396e IDE suggestions 2024-05-19 09:07:20 +01:00
Adrian Conlon
291a212504 Ugrade to .NET 8.0: First pass 2024-05-18 21:57:33 +01:00
Adrian Conlon
47ecdad3e8 Work towards accurate bus/memory/io timings. Especially Z80 m-cycle timing. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2020-07-05 00:09:51 +01:00
Adrian Conlon
cd4af67177 Work my way through a bunch of the analysis suggestions. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2020-06-22 00:00:15 +01:00
Adrian Conlon
db0e8c613f Update all analysis (and other!) nuget packages, ensure builds across all projects. 
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
 2020-06-21 18:35:10 +01:00
Adrian Conlon
2becf0e220 Apply any analysis suggestions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-12-04 23:23:48 +00:00
Adrian Conlon
73d08fe7a7 Upgrade .net version and analysis packages en mass. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-12-04 01:03:17 +00:00
Adrian Conlon
3a40d0103a Update some framework and analysis versions. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-12-03 23:01:09 +00:00
Adrian Conlon
c15ec96862 Make the Z80 implementation M-Cycle accurate. I think! 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-30 14:06:38 +00:00
Adrian Conlon
c7c9963db3 Actually, the refresh register is incremented halfway through M1, as the M1 pin is raised. i.e. just before the refresh phase of the M1 cycle. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-16 22:29:42 +00:00
Adrian Conlon
3c87907471 Choose a different mechanism for ignoring (at the moment) bus test events. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-16 21:00:26 +00:00
Adrian Conlon
ac56257558 Whoops: Z80: missed raising the INT pin, after it been acknowledged. 
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
 2019-11-16 20:58:52 +00:00