 Adrian Conlon
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a8ef9aa7db
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simplification and unification of build stuff
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2026-02-16 11:15:58 +00:00 |
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Adrian Conlon
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e1bf58afbc
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More sharing of concepts between all Intel style processors
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2026-01-03 23:17:30 +00:00 |
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Adrian Conlon
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1dfd9621a1
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Share some more common code between Intel style procesors
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2025-10-15 19:46:10 +01:00 |
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Adrian Conlon
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ceacac4741
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Fix up some oddities in the EightBit library
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2025-10-06 13:44:31 +01:00 |
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Adrian Conlon
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1779d1dc40
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Intel processors all seem to act slightly differently with regards to HALT
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2025-08-17 12:03:51 +01:00 |
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Adrian Conlon
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c67e376d4f
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Add support for checking deferred EI correctness
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2025-08-14 14:57:51 +01:00 |
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Adrian Conlon
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25ca534186
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The EI instructions is actually a deferred instruction
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2025-08-10 21:47:15 +01:00 |
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Adrian Conlon
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558da38f12
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Note commonality between Intel-style processors
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2025-08-10 12:43:34 +01:00 |
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Adrian Conlon
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14e4132d34
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Small consistency change
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2025-08-06 16:54:14 +01:00 |
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Adrian Conlon
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9d208de9bb
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Explicitly state order of operations in code, rather than relying upon RAII etc. (for speed. Much faster)
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2025-08-04 15:47:26 +01:00 |
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Adrian Conlon
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60ef099208
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Tidy some inconsistencies in various emulation
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2025-08-01 15:01:20 +01:00 |
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Adrian Conlon
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2f338c6c46
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Tidy register increment/decrement a little.
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2025-07-25 16:32:30 +01:00 |
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 Adrian Conlon
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36e983526e
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Add increment/decrement operations to the Register16 class
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2025-05-11 19:24:40 +01:00 |
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Adrian Conlon
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e1696721f6
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Simplifications and refactorings in th intel processors
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2025-05-05 21:06:39 +01:00 |
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Adrian Conlon
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93e09c192f
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Share instruction fetch and halt implementations
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2025-05-04 11:41:28 +01:00 |
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Adrian Conlon
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2336222c97
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Push more core processor handling into base classes.
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2025-05-04 10:53:23 +01:00 |
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Adrian Conlon
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47374e591d
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With my correct implementation of HALT, I need the fetch to take place during a halted state
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2025-05-04 08:56:22 +01:00 |
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Adrian Conlon
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cbe871d365
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Isolate program counter increment/decrement (to be used for HALT processing)
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2025-05-03 23:25:06 +01:00 |
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Adrian Conlon
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080f203a55
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Unify Intel style JR CC code and fix SM83 timing issues.
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2025-05-03 12:09:34 +01:00 |
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Adrian Conlon
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0679b95b77
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Correct LR35902 HALT test. Whatever problems this has, won't be solved by a hack
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2025-05-03 11:58:57 +01:00 |
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Adrian Conlon
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e1aa220409
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Further Z80 timing fixes: 290 failures
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2025-05-03 00:09:19 +01:00 |
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Adrian Conlon
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dd1d141f15
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Simplify conditional flag handling in intel processors
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2025-04-29 12:27:39 +01:00 |
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Adrian Conlon
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973590690c
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Fix a bunch of analysis issues
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2025-04-01 09:32:29 +01:00 |
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Adrian Conlon
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87abbaa75e
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Tidy IO page access
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2025-03-28 14:50:53 +00:00 |
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Adrian Conlon
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fa48a64cac
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Take advantage of some simplifications
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2025-03-28 09:17:09 +00:00 |
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Adrian Conlon
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3a9e89f009
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Tidy a couple of IO effects in the LR35902 core
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2025-03-28 09:03:32 +00:00 |
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Adrian Conlon
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4d0059ad94
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Only 7 failing instructions now
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2025-03-27 14:34:54 +00:00 |
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Adrian Conlon
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3ca3d60caf
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Correct some timing issues in GB core
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2025-03-27 10:19:18 +00:00 |
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Adrian Conlon
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08089823c2
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First stab at getting LR35902 HarteTests running. Not bad, so far!
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2025-03-26 21:16:37 +00:00 |
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Adrian Conlon
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f31442511f
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LR35902 analysis suggestions
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2025-01-26 21:17:07 +00:00 |
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Adrian Conlon
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4b4181e12d
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Synchonise with unmanaged GB implementation
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2024-10-14 11:04:51 +01:00 |
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Adrian Conlon
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fa13852e53
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Sort out GB timing (enough to pass Blargg, anyway)
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2024-10-12 14:38:45 +01:00 |
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Adrian Conlon
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0bc3cb9d03
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first round of .net 9 analysis
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2024-10-12 13:15:14 +01:00 |
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Adrian Conlon
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b38462bddf
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.net 9 gb analysis changes
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2024-10-12 12:57:38 +01:00 |
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Adrian Conlon
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90c887d169
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Use intrinsics, if possible
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2024-08-05 20:32:34 +01:00 |
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Adrian Conlon
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c8ac0f20dc
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Step can be split a little to make it easier to override.
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2024-07-24 17:21:49 +01:00 |
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Adrian Conlon
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d8fad7b988
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Try to minimise use of "Word" from Register16
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2024-06-30 12:30:07 +01:00 |
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Adrian Conlon
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a64f370d7c
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Compilation fixes
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2024-05-29 10:56:16 +01:00 |
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Adrian Conlon
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47ecdad3e8
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Work towards accurate bus/memory/io timings. Especially Z80 m-cycle timing.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2020-07-05 00:09:51 +01:00 |
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Adrian Conlon
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cd4af67177
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Work my way through a bunch of the analysis suggestions.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2020-06-22 00:00:15 +01:00 |
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Adrian Conlon
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bc491884b0
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Synchronise HALT implementation for Intel style processors with the C++ version.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-29 09:05:31 +01:00 |
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Adrian Conlon
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583c5444a0
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Correct a couple of small LR35902 timing issues.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-12 18:33:33 +01:00 |
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Adrian Conlon
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f54ef07057
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Couple of small refactorings, based on repeated bit patterns
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-07 13:27:03 +01:00 |
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Adrian Conlon
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5a7a3b5019
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Tidy up EightBit.GameBoy namespace definition.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-28 11:50:25 +01:00 |
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Adrian Conlon
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af82470f27
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Correct a couple of LR35902 timing mistakes.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-27 10:24:03 +01:00 |
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Adrian Conlon
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800eff05a6
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Correct AF value in LR35902 emulator
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-26 00:58:54 +01:00 |
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Adrian Conlon
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8dea5746c4
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Tidy up stylecopy usage for the LR35902 set of libraries.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-21 13:11:00 +01:00 |
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Adrian Conlon
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b6ced1ddd5
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Use "InvalidOperationException" for invalid opcodes in LR35902 emulation (for Fuse test runner)
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-19 23:58:26 +01:00 |
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Adrian Conlon
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7f30fcf4b2
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Whoops: extra blank link crept in.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-14 17:49:35 +01:00 |
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Adrian Conlon
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3eb3975e37
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Add an initial stab at LR35902 (aka GameBoy) support. Untested and no disassembler though...
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-14 17:46:57 +01:00 |
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