526 Commits

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Author	SHA1	Message	Date
Adrian Conlon	b5f646c641	Better arrangement of decimal SBC/ADC implementations	2026-05-15 22:50:11 +01:00
Adrian Conlon	6d4d2f22e2	Needs tidying a little by full cycle accuracy for 6502 / 65c02	2026-05-15 22:02:03 +01:00
Adrian Conlon	8f59e79959	Add explicit NOPs to the MOS 6502 implementation	2026-05-14 15:17:41 +01:00
Adrian Conlon	ac200d7f76	Simplify ignored return value handling	2026-05-12 22:21:13 +01:00
Adrian Conlon	a98b904207	Whoops: missed one more test	2026-05-12 22:19:11 +01:00
Adrian Conlon	f1fb442f08	Add 6809 Schwotzer tests	2026-05-12 22:18:51 +01:00
Adrian Conlon	b228332e27	Tidy up old debugging changes	2026-05-12 20:23:42 +01:00
Adrian Conlon	96eaf1b22f	Update interrupt timing	2026-05-12 15:23:45 +01:00
Adrian Conlon	75a07ceea0	Add a little more documentation	2026-05-12 11:45:41 +01:00
Adrian Conlon	83ee80edcf	Make addressing mode handling more consistent on 6502 implementation	2026-05-12 11:44:42 +01:00
Adrian Conlon	d7e3ea0ef3	Use underscored private member variables	2026-05-11 23:07:34 +01:00
Adrian Conlon	fc1ad39a8d	Add half-carry tests	2026-05-11 22:27:30 +01:00
Adrian Conlon	37ed8b4d11	Increment shouldn't affect the half-carry flag	2026-05-11 22:20:10 +01:00
Adrian Conlon	9f62175e06	Enhance "TST" tests	2026-05-11 22:04:39 +01:00
Adrian Conlon	f6ee25c5f9	Fix "TST" implementation	2026-05-11 21:59:13 +01:00
Adrian Conlon	e1470a13fa	Simplify 6809 boolean flag handling	2026-05-11 19:18:11 +01:00
Adrian Conlon	f01762b9de	Fix a small effective address problem	2026-05-11 17:30:38 +01:00
Adrian Conlon	f1c02dd012	Simplify long/short branch	2026-05-11 14:59:06 +01:00
Adrian Conlon	0e48e86edf	Correct LBSR implementation	2026-05-11 14:53:22 +01:00
Adrian Conlon	1dfa94daf2	Small tidy ups	2026-05-11 14:37:54 +01:00
Adrian Conlon	ad97013127	Isolate effecitive address usage away from "intermediate" usage	2026-05-11 13:59:46 +01:00
Adrian Conlon	71d7832e91	Sort out inherent addressing to be a little more consistent	2026-05-11 13:10:56 +01:00
Adrian Conlon	fa61bd4854	Update documentation links, including some wayback machinem for unavailable	2026-05-10 09:57:02 +01:00
Adrian Conlon	5026c27582	Correct performance issue in "board" by fixing uncontrolled MemoryMapping allocations.	2026-05-09 18:23:13 +01:00
Adrian Conlon	da7f362754	Fix ASR implementation. Unify ANDCC / ORCC cycle waste	2026-05-09 17:31:05 +01:00
Adrian Conlon	1c485bca22	Correct all obvious timing inaccuracies	2026-05-09 17:15:11 +01:00
Adrian Conlon	a9f2049c17	Current cycle checks/updates	2026-05-09 15:30:01 +01:00
Adrian Conlon	f093bf1e53	Work in progress	2026-05-09 14:11:07 +01:00
Adrian Conlon	b175086307	Mild overloading refactor for 6809	2026-05-07 20:43:30 +01:00
Adrian Conlon	224fe74e09	Refactor 6809 processor for readability	2026-05-07 17:11:42 +01:00
Adrian Conlon	95b801b72f	Correct a couple of anomolies in 6809 core	2026-05-05 21:29:10 +01:00
Adrian Conlon	d5b92b01c9	Tidy up everything I can see in 6809 implementation to bring it into line.	2026-05-05 19:19:13 +01:00
Adrian Conlon	2bb004598e	Simplify parity adjustment in block IO repeat code.	2026-05-03 11:37:02 +01:00
Adrian Conlon	88d4ab5126	Fix final 4 opcodes for 100% harte singlestep test compatibility. hurrah!	2026-05-03 11:27:14 +01:00
Adrian Conlon	69a0865ee9	Start work towards WDC 65C02 implementation	2026-05-02 17:02:36 +01:00
Adrian Conlon	10106657d3	Some small cosmetic changes	2026-05-02 14:13:01 +01:00
Adrian Conlon	fa73a86121	Fix theoretical symbols parser issue	2026-05-02 13:47:44 +01:00
Adrian Conlon	cfc3169933	So there we have it. 100% Harte single step coverage/success for MOS 6502	2026-05-02 13:47:04 +01:00
Adrian Conlon	de12029c13	Speedup Z80 by encouraging runtime inlining of code	2026-04-20 18:56:05 +01:00
Adrian Conlon	699791f7a4	Simplify intermediate 16-bit register usage	2026-04-16 13:47:24 +01:00
Adrian Conlon	53e33b9eef	Some simplifications	2026-04-07 12:02:31 +01:00
Adrian Conlon	284158247b	Fix up 6502 test classes	2026-03-31 21:52:20 +01:00
Adrian Conlon	bb626b9e9e	Simplify some memory update calls	2026-03-27 18:19:08 +00:00
Adrian Conlon	47baff3740	Correct some 8080 timing mistakes	2026-03-27 18:16:09 +00:00
Adrian Conlon	c587da19c4	Interesting. At best agressive inlining had zero effect and may have slowed things down slightly	2026-03-27 18:15:02 +00:00
Adrian Conlon	290f7583c5	Correct region mis-label	2026-03-27 18:14:24 +00:00
Adrian Conlon	98448b0524	Small consistency changes for LR35902 core	2026-03-21 12:44:19 +00:00
Adrian Conlon	45a57eea86	Coupld of small readability changes	2026-03-21 09:49:09 +00:00
Adrian Conlon	0029427d6f	Fix 8080 implementation to be closer to Z80	2026-03-21 09:48:35 +00:00
Adrian Conlon	dcd98e5eb7	Simplify Z80 IM2 implementation	2026-03-20 09:55:40 +00:00