91 Commits

Author	SHA1	Message	Date
Adrian Conlon	3bbf300e05	Simplify switching processor pin handling	2025-06-22 21:07:02 +01:00
Adrian Conlon	e7b025e66e	Some speed-up refactoring of the Z80 core	2025-05-12 10:17:39 +01:00
Adrian Conlon	36e983526e	Add increment/decrement operations to the Register16 class	2025-05-11 19:24:40 +01:00
Adrian Conlon	9e0006187e	Port access in Intel processors is 16 rather than 8 bit addressed	2025-05-08 13:00:30 +01:00
Adrian Conlon	79c15602eb	Small refactor	2025-05-07 21:27:01 +01:00
Adrian Conlon	293c735ec5	Simplify indirect memory access	2025-05-07 11:56:23 +01:00
Adrian Conlon	1a09473b5a	Read port refactoring	2025-05-06 23:05:51 +01:00
Adrian Conlon	a6051a64ab	More IO simplifications	2025-05-06 22:51:30 +01:00
Adrian Conlon	62f42ef46f	Refactored a little, but no functional changes	2025-05-06 21:41:32 +01:00
Adrian Conlon	95783d37aa	Reset/power refactoring for z80	2025-05-06 15:37:24 +01:00
Adrian Conlon	d58095a9d0	Power-on and reset consistency fixes	2025-05-06 11:52:33 +01:00
Adrian Conlon	e1696721f6	Simplifications and refactorings in th intel processors	2025-05-05 21:06:39 +01:00
Adrian Conlon	37431d08bc	Correct LD?R/CP?R block methods. 4 problem instuctions now.	2025-05-04 17:47:19 +01:00
Adrian Conlon	045907e273	Fix INI/IND flag handling. 8 problems remaining	2025-05-04 17:22:23 +01:00
Adrian Conlon	6d84c3a41f	Get SCF/CCF X/Y flags working correctly. 10 problems reported now.	2025-05-04 16:00:08 +01:00
Adrian Conlon	93e09c192f	Share instruction fetch and halt implementations	2025-05-04 11:41:28 +01:00
Adrian Conlon	2336222c97	Push more core processor handling into base classes.	2025-05-04 10:53:23 +01:00
Adrian Conlon	853569b2ca	Isolate REFRESH pin functionality	2025-05-04 00:35:14 +01:00
Adrian Conlon	cbe871d365	Isolate program counter increment/decrement (to be used for HALT processing)	2025-05-03 23:25:06 +01:00
Adrian Conlon	2501bdfd28	More block timing issues corrected. 16 issues remaining	2025-05-03 22:46:02 +01:00
Adrian Conlon	6d8a00876f	Fix a bunch of "block" instruction timings. 16 problems remaining.	2025-05-03 19:51:36 +01:00
Adrian Conlon	26457b4a77	Correct timing for 16-bit arithmetic tests. 26 failures remaining	2025-05-03 15:03:04 +01:00
Adrian Conlon	68328d92fb	Fix displaced timing on arithmetic operations for z80. 34 failures now	2025-05-03 14:40:38 +01:00
Adrian Conlon	506e2b9eda	Fix some displaced memory load timing issues. 50 issues remaining.	2025-05-03 14:10:18 +01:00
Adrian Conlon	f9754dd62f	Fix some z80 eight-bit load timing issues. 58 issues remaining	2025-05-03 13:54:18 +01:00
Adrian Conlon	9f2079efae	More z80 timing issues fixed. 70 issues remain	2025-05-03 13:21:36 +01:00
Adrian Conlon	080f203a55	Unify Intel style JR CC code and fix SM83 timing issues.	2025-05-03 12:09:34 +01:00
Adrian Conlon	94b8da456b	Fix loads of z80 timing issues. 84 timing issues remain.	2025-05-03 11:45:55 +01:00
Adrian Conlon	946121defb	Fix HALT instruction	2025-05-03 02:08:52 +01:00
Adrian Conlon	561483d65d	More timing fixes. 255 timing errors	2025-05-03 01:31:44 +01:00
Adrian Conlon	f4f4357a3e	More z80 timing fixes, 261 errors	2025-05-03 00:51:20 +01:00
Adrian Conlon	e1aa220409	Further Z80 timing fixes: 290 failures	2025-05-03 00:09:19 +01:00
Adrian Conlon	175069d6bf	More Z80 timing fixes	2025-05-02 20:18:04 +01:00
Adrian Conlon	3617608e8c	Fix a number of write timing issues	2025-05-02 17:46:33 +01:00
Adrian Conlon	fda52af260	Only DJNZ has the extra tick (presumably to decrement the B register)	2025-05-02 14:07:15 +01:00
Adrian Conlon	935466ad6f	Correct timing issues both conditional and unconditional relative jumpson Z80	2025-05-02 14:03:15 +01:00
Adrian Conlon	9670c3fd21	Start correcting timing issues in my Z80 implementation	2025-05-02 12:11:54 +01:00
Adrian Conlon	dd1d141f15	Simplify conditional flag handling in intel processors	2025-04-29 12:27:39 +01:00
Adrian Conlon	1b1b92ac2c	More event handling simplification	2025-03-29 13:18:54 +00:00
Adrian Conlon	3d6b549c76	Turns out using lambdas to control pins is lovely and correct, but terribly slow. Back to a more traditional method.	2025-03-24 20:18:04 +00:00
Adrian Conlon	d4dc99b454	Use lambda functions to simplify CPU pin control	2025-03-23 11:08:36 +00:00
Adrian Conlon	a9db2f58bd	miscellaneous fixes, especiall flags	2025-03-18 18:38:47 +00:00
Adrian Conlon	e8d770c6bb	Simplify i/o port handling in Z80 implementation	2025-01-27 21:23:47 +00:00
Adrian Conlon	f6829f2ec0	Z80 .net 9 analysis changes	2024-10-12 12:09:22 +01:00
Adrian Conlon	3cbc7f32d2	More analysis fixes	2024-10-09 22:46:25 +01:00
Adrian Conlon	647be6f224	More style changes	2024-10-09 21:16:55 +01:00
Adrian Conlon	d67cafe297	Prefer a more straightforward register exchange	2024-09-27 12:43:14 +01:00
Adrian Conlon	c8ac0f20dc	Step can be split a little to make it easier to override.	2024-07-24 17:21:49 +01:00
Adrian Conlon	ee584867c2	Modernise some more c# code	2024-07-18 11:38:02 +01:00
Adrian Conlon	d80f340081	Simplfy access to Z80 registers	2024-07-04 08:47:53 +01:00