 Adrian Conlon
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558da38f12
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Note commonality between Intel-style processors
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2025-08-10 12:43:34 +01:00 |
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Adrian Conlon
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3a8e379efd
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Align with Z80 implementation
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2025-08-07 09:42:52 +01:00 |
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Adrian Conlon
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60ef099208
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Tidy some inconsistencies in various emulation
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2025-08-01 15:01:20 +01:00 |
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Adrian Conlon
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2f338c6c46
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Tidy register increment/decrement a little.
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2025-07-25 16:32:30 +01:00 |
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 Adrian Conlon
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36e983526e
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Add increment/decrement operations to the Register16 class
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2025-05-11 19:24:40 +01:00 |
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Adrian Conlon
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19c18445d6
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Remove a couple of pointless "Word"isms
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2025-05-08 19:46:43 +01:00 |
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Adrian Conlon
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9e0006187e
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Port access in Intel processors is 16 rather than 8 bit addressed
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2025-05-08 13:00:30 +01:00 |
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Adrian Conlon
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db1da4f506
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Remove extra line
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2025-05-06 21:39:47 +01:00 |
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Adrian Conlon
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e1696721f6
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Simplifications and refactorings in th intel processors
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2025-05-05 21:06:39 +01:00 |
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Adrian Conlon
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93e09c192f
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Share instruction fetch and halt implementations
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2025-05-04 11:41:28 +01:00 |
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Adrian Conlon
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2336222c97
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Push more core processor handling into base classes.
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2025-05-04 10:53:23 +01:00 |
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Adrian Conlon
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cbe871d365
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Isolate program counter increment/decrement (to be used for HALT processing)
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2025-05-03 23:25:06 +01:00 |
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Adrian Conlon
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dd1d141f15
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Simplify conditional flag handling in intel processors
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2025-04-29 12:27:39 +01:00 |
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Adrian Conlon
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1b1b92ac2c
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More event handling simplification
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2025-03-29 13:18:54 +00:00 |
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Adrian Conlon
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b1b050b1d3
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.net 9 analysis changes
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2024-10-12 11:09:29 +01:00 |
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Adrian Conlon
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f525fcf412
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Apply .net 9 analysis changes
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2024-10-12 09:44:39 +01:00 |
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Adrian Conlon
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c8ac0f20dc
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Step can be split a little to make it easier to override.
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2024-07-24 17:21:49 +01:00 |
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Adrian Conlon
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d8fad7b988
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Try to minimise use of "Word" from Register16
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2024-06-30 12:30:07 +01:00 |
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Adrian Conlon
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a64f370d7c
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Compilation fixes
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2024-05-29 10:56:16 +01:00 |
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Adrian Conlon
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47ecdad3e8
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Work towards accurate bus/memory/io timings. Especially Z80 m-cycle timing.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2020-07-05 00:09:51 +01:00 |
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Adrian Conlon
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cd4af67177
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Work my way through a bunch of the analysis suggestions.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2020-06-22 00:00:15 +01:00 |
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Adrian Conlon
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bc491884b0
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Synchronise HALT implementation for Intel style processors with the C++ version.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-29 09:05:31 +01:00 |
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Adrian Conlon
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0dd6f1025f
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Simplify 8080/Z80 XHTL implementation.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-28 23:18:08 +01:00 |
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Adrian Conlon
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e35dabd130
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Fuse fixes: Correct bus read/write order of XHTL
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-08-15 14:31:23 +01:00 |
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Adrian Conlon
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d0c620e709
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Use MEMPTR, rather than an i8080 specific intermediate register.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-14 17:36:03 +01:00 |
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Adrian Conlon
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853b6e2b08
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Correct some straightforward analysis issues.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-07-01 00:15:25 +01:00 |
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Adrian Conlon
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1d976e811d
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Introduce a little consistency with regards to pin naming and usage.
Signed-off-by: Adrian Conlon <adrian.conlon@gmail.com>
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2019-04-23 00:58:33 +01:00 |
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Adrian Conlon
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e80963260d
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Try to avoid copying around Register16 references, if possible.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-03-07 01:21:00 +00:00 |
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Adrian Conlon
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4799e097de
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Update stylecop (plus add stylecop packages to the Intel 8080 set).
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-03-02 08:59:20 +00:00 |
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Adrian Conlon
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9a1d5cc762
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First commit of the Intel8080 processor core. Passes diagnostics. Runs at ~50% speed of unmanaged code.
Signed-off-by: Adrian Conlon <Adrian.conlon@gmail.com>
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2019-02-28 00:06:35 +00:00 |
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