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Author	SHA1	Message	Date
Adrian Conlon	c67e376d4f	Add support for checking deferred EI correctness	2025-08-14 14:57:51 +01:00
Adrian Conlon	4da07a8fa2	Correct interrupt flag checks in Gameboy checker	2025-08-14 11:18:02 +01:00
Adrian Conlon	a4e704fef4	I give up. This is probably more compatible with Intel derived processors	2025-08-13 19:03:25 +01:00
Adrian Conlon	7951abde00	Add support for "Gameboy Doctor" log checker.	2025-08-13 14:01:14 +01:00
Adrian Conlon	eb23fbe44c	Correction: the least significant bit is *not* zeroed by an IM 2 interrupt	2025-08-12 17:19:55 +01:00
Adrian Conlon	e96a51342a	Remove unneeded "using"	2025-08-12 08:28:08 +01:00
Adrian Conlon	25ca534186	The EI instructions is actually a deferred instruction	2025-08-10 21:47:15 +01:00
Adrian Conlon	d4775cb266	Correct assertion failure during refresh cycle	2025-08-10 12:52:48 +01:00
Adrian Conlon	558da38f12	Note commonality between Intel-style processors	2025-08-10 12:43:34 +01:00
Adrian Conlon	2e1573b016	Add support for sub-M-cycle accuracy. Not sure how useful this is!	2025-08-10 11:32:53 +01:00
Adrian Conlon	072e38f6ee	Add a couple of debug assertions	2025-08-09 15:10:27 +01:00
Adrian Conlon	b40224b5af	Correct IM 2 indirection	2025-08-09 14:52:41 +01:00
Adrian Conlon	f1febd480e	Sort out interrupt timing (I think)	2025-08-09 13:29:57 +01:00
Adrian Conlon	e8a1e7dc6e	Sort out Z80/Spectrum pin handling (again!)	2025-08-08 21:47:48 +01:00
Adrian Conlon	199d0a77b1	Disable interrups as the first act of INT handling	2025-08-08 00:03:21 +01:00
Adrian Conlon	41be64ad99	Simplfy interrupts on Z80	2025-08-07 19:05:41 +01:00
Adrian Conlon	d332c57e47	Simplify Z80 port handling	2025-08-07 09:56:25 +01:00
Adrian Conlon	3a8e379efd	Align with Z80 implementation	2025-08-07 09:42:52 +01:00
Adrian Conlon	ed6c7968bd	Remove effectively impossible to use methods	2025-08-07 09:42:23 +01:00
Adrian Conlon	14e4132d34	Small consistency change	2025-08-06 16:54:14 +01:00
Adrian Conlon	350483fcec	Catch another couple of Z80 timing issues	2025-08-05 00:14:05 +01:00
Adrian Conlon	796042acdf	Simplfy intel processor interations	2025-08-04 19:47:40 +01:00
Adrian Conlon	52ea4b3acd	Last trivial Z80 update	2025-08-04 18:19:40 +01:00
Adrian Conlon	9d208de9bb	Explicitly state order of operations in code, rather than relying upon RAII etc. (for speed. Much faster)	2025-08-04 15:47:26 +01:00
Adrian Conlon	319190b7a5	More Z80 cycle simplifications and fixes	2025-08-03 21:55:24 +01:00
Adrian Conlon	6a32d0269d	Fix the Z80 checker, so that all cycle actions are checked.	2025-08-03 21:54:05 +01:00
Adrian Conlon	3ccd9c45ca	Adjusted for the latest single-step Z80 tests. Simplify memory update access.	2025-08-02 17:49:18 +01:00
Adrian Conlon	bfc2355337	Correct RRD/RLD timing and XHTL ordering (according to latest Z80 single step tests)	2025-08-02 12:26:53 +01:00
Adrian Conlon	6143a9d285	Hack to allow single step tests to completely work: disable IO area triggers.	2025-08-01 22:59:00 +01:00
Adrian Conlon	bb63211f17	Fix event names	2025-08-01 22:57:38 +01:00
Adrian Conlon	60ef099208	Tidy some inconsistencies in various emulation	2025-08-01 15:01:20 +01:00
Adrian Conlon	a252a74d2d	Tidy some inconsistencies in z80 emulation	2025-08-01 14:59:40 +01:00
Adrian Conlon	2f338c6c46	Tidy register increment/decrement a little.	2025-07-25 16:32:30 +01:00
Adrian Conlon	c271b28495	Simplify bus addressing	2025-07-05 09:46:59 +01:00
Adrian Conlon	3bbf300e05	Simplify switching processor pin handling	2025-06-22 21:07:02 +01:00
Adrian Conlon	3105930027	Fix BBR/BBS timings in 65C02	2025-06-19 13:27:05 +01:00
Adrian Conlon	caca3467d9	More unit test stuff. New tests generated by copilot	2025-05-13 09:52:12 +01:00
Adrian Conlon	12053fd076	Tidy 6809 tests namespace	2025-05-12 21:39:42 +01:00
Adrian Conlon	a5eed89b26	Tidy up all the 6809 stuff	2025-05-12 21:08:39 +01:00
Adrian Conlon	6e1fc14530	Start tidying up 6809 implementation/testst	2025-05-12 19:15:34 +01:00
Adrian Conlon	adbd16daa2	Get M6809 unit tests running again	2025-05-12 12:19:27 +01:00
Adrian Conlon	e7b025e66e	Some speed-up refactoring of the Z80 core	2025-05-12 10:17:39 +01:00
Adrian Conlon	8331b4818e	Couple of small Register16 adjustments	2025-05-11 21:30:15 +01:00
Adrian Conlon	36e983526e	Add increment/decrement operations to the Register16 class	2025-05-11 19:24:40 +01:00
Adrian Conlon	60d000905f	Remove a bunch of analysis warnings	2025-05-08 22:03:27 +01:00
Adrian Conlon	fc2b0470a3	Remove test patterns	2025-05-08 22:01:19 +01:00
Adrian Conlon	19c18445d6	Remove a couple of pointless "Word"isms	2025-05-08 19:46:43 +01:00
Adrian Conlon	d92926c15b	Quite a fun low level rearrangement of the 16-bit register class.	2025-05-08 19:46:08 +01:00
Adrian Conlon	9e0006187e	Port access in Intel processors is 16 rather than 8 bit addressed	2025-05-08 13:00:30 +01:00
Adrian Conlon	eda9519068	Correct some analysis issues	2025-05-07 21:30:19 +01:00