 Adrian Conlon
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5a670ba718
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A few miscellaneous changes
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2026-06-21 08:53:16 +01:00 |
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Adrian Conlon
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6114a3ab92
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Whoops: missed lower level changes
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2026-06-18 21:49:18 +01:00 |
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Adrian Conlon
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27b3e0354b
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Add logging levels to IntelHexFile loader
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2026-06-17 21:33:49 +01:00 |
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Adrian Conlon
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c745af2dfa
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Add more checks/logging. Also make checks optional in a "strict" mode, to allow problematic files to still load, if possible.
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2026-06-17 13:32:35 +01:00 |
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Adrian Conlon
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486014e48d
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Simplify Intel HEX file parsing a little
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2026-06-16 16:31:27 +01:00 |
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Adrian Conlon
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2fd16b84bb
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Improve Intel HEX file parsing. Should be OK, according to wikipedia, anyway!
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2026-06-16 12:26:56 +01:00 |
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Adrian Conlon
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24d6c0c5fa
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Test harness timer limited to *just* CPU run timings
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2026-06-15 12:28:56 +01:00 |
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Adrian Conlon
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25dcb0c4c0
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More straightforward to read test harness results
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2026-06-14 21:53:56 +01:00 |
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Adrian Conlon
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b9b1b96c42
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Cycles count needs to be correct per clock tick
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2026-06-10 20:12:24 +01:00 |
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Adrian Conlon
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39561437e9
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More performance improvements
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2026-06-10 17:26:26 +01:00 |
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Adrian Conlon
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552de802fe
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Performance changes (mainly for Z80)
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2026-06-10 15:23:19 +01:00 |
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Adrian Conlon
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7d99e8162f
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Small usage simplification with bus mapper
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2026-06-01 11:10:31 +01:00 |
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Adrian Conlon
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2d145ec023
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No need for bus read/write events with cycle accurate cpu read/write events
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2026-05-29 10:17:40 +01:00 |
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Adrian Conlon
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7c2c7a1973
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Closer to C++ clocked chip implementation
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2026-05-28 18:19:34 +01:00 |
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Adrian Conlon
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110c68a54e
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Some small consistency changes. Interesting!
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2026-05-28 18:01:33 +01:00 |
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Adrian Conlon
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c191639a24
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Simplify some exception throwing logic
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2026-05-26 21:00:47 +01:00 |
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Adrian Conlon
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04f798fba9
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Bus readonly write tests/changes
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2026-05-25 13:13:52 +01:00 |
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Adrian Conlon
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932bcfd54e
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Some small consistency tidyups.
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2026-05-24 22:48:34 +01:00 |
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Adrian Conlon
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ec59b422b9
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Simplify PC increment/decrement a little
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2026-05-21 16:35:20 +01:00 |
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Adrian Conlon
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37fc258d47
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Some simplifications
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2026-05-21 11:57:52 +01:00 |
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Adrian Conlon
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291266e4fc
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Assert that which needs to be checked, but not thrown
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2026-05-21 10:00:57 +01:00 |
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Adrian Conlon
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608fbb55fb
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Couple of small tidy ups
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2026-05-18 20:46:42 +01:00 |
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Adrian Conlon
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dfd4d1928f
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Make "Pop" more like "Read". i.e. don't return a result, just use the value placed on the "bus"
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2026-05-18 18:24:32 +01:00 |
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Adrian Conlon
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741feb4342
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Performance change: avoid dropping Bus.Data return values
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2026-05-18 17:28:41 +01:00 |
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Adrian Conlon
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b8e95f52b3
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Inline clock ticking mechanism
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2026-05-17 10:27:34 +01:00 |
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Adrian Conlon
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072a8dd984
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Blargg tests run again. Corrected speed issue of MemoryMappings being created too often and bus data being trashed by a write to ROM.
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2026-05-17 09:50:12 +01:00 |
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Adrian Conlon
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9a011b3c57
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Start implementing HD6309. Introduction of 32-bit operations has forced me to rename some of "Word" methods to better indicate size
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2026-05-16 21:10:23 +01:00 |
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Adrian Conlon
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ab835297fd
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Couple of small tidy ups
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2026-05-16 13:50:14 +01:00 |
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Adrian Conlon
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e0fffdaa5e
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Some performance improvements. About 50Mhz for Z80 emulator. 275Mhz to 325Mhz. Interesting.
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2026-05-16 11:09:03 +01:00 |
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Adrian Conlon
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ac200d7f76
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Simplify ignored return value handling
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2026-05-12 22:21:13 +01:00 |
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Adrian Conlon
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69a0865ee9
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Start work towards WDC 65C02 implementation
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2026-05-02 17:02:36 +01:00 |
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Adrian Conlon
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de12029c13
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Speedup Z80 by encouraging runtime inlining of code
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2026-04-20 18:56:05 +01:00 |
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Adrian Conlon
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699791f7a4
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Simplify intermediate 16-bit register usage
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2026-04-16 13:47:24 +01:00 |
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Adrian Conlon
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53e33b9eef
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Some simplifications
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2026-04-07 12:02:31 +01:00 |
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Adrian Conlon
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47baff3740
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Correct some 8080 timing mistakes
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2026-03-27 18:16:09 +00:00 |
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Adrian Conlon
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c587da19c4
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Interesting. At best agressive inlining had zero effect and may have slowed things down slightly
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2026-03-27 18:15:02 +00:00 |
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Adrian Conlon
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290f7583c5
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Correct region mis-label
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2026-03-27 18:14:24 +00:00 |
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Adrian Conlon
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a8ef9aa7db
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simplification and unification of build stuff
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2026-02-16 11:15:58 +00:00 |
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Adrian Conlon
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810d05a50e
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tidy the intel op-code decoder a little
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2025-11-27 16:49:44 +00:00 |
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Adrian Conlon
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1dfd9621a1
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Share some more common code between Intel style procesors
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2025-10-15 19:46:10 +01:00 |
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Adrian Conlon
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33fce45cc8
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Some performance updates
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2025-10-13 17:36:32 +01:00 |
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Adrian Conlon
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ceacac4741
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Fix up some oddities in the EightBit library
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2025-10-06 13:44:31 +01:00 |
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Adrian Conlon
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1779d1dc40
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Intel processors all seem to act slightly differently with regards to HALT
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2025-08-17 12:03:51 +01:00 |
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Adrian Conlon
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a4e704fef4
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I give up. This is probably more compatible with Intel derived processors
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2025-08-13 19:03:25 +01:00 |
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Adrian Conlon
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558da38f12
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Note commonality between Intel-style processors
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2025-08-10 12:43:34 +01:00 |
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Adrian Conlon
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e8a1e7dc6e
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Sort out Z80/Spectrum pin handling (again!)
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2025-08-08 21:47:48 +01:00 |
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Adrian Conlon
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41be64ad99
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Simplfy interrupts on Z80
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2025-08-07 19:05:41 +01:00 |
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Adrian Conlon
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d332c57e47
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Simplify Z80 port handling
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2025-08-07 09:56:25 +01:00 |
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Adrian Conlon
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ed6c7968bd
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Remove effectively impossible to use methods
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2025-08-07 09:42:23 +01:00 |
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Adrian Conlon
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796042acdf
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Simplfy intel processor interations
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2025-08-04 19:47:40 +01:00 |
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