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Clipping optimizations
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@ -206,14 +206,16 @@ asm _clipX#0
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BCS INVISX ; YEP, X OFF RIGHT EDGE
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;CLC
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ADC ESTKL-3,X ; X + WIDTH
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CMP TMPL ; < DST_WIDTH?
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BCC VISX ; YEP, FULLY VISIBLE
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LDA TMPL ; CLIP WIDTH TO DST_WIDTH
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CMP TMPL ; >= DST_WIDTH?
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BCS +
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LDA #$00 ; FULLY VISIBLE
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RTS
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+ LDA TMPL ; CLIP WIDTH TO DST_WIDTH
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;SEC
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SBC ESTKL-1,X
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STA ESTKL-3,X ; WIDTH = DST_WIDTH - X
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VISX LDA #$00 ; FULLY VISIBLE
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CLC
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LDA #$00 ; VISIBLE WITH WIDTH CLIP
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RTS
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; X NEGATIVE, CHECK WITH W ADDED
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NEGX LDA ESTKL-1,X ; X COORD
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@ -252,14 +254,16 @@ asm _clipY#0
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BCS INVISY ; YEP, Y OFF BOTTOM EDGE
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;CLC
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ADC ESTKL-4,X ; Y + HEIGHT
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CMP TMPL ; < DST_HEIGHT
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BCC VISY ; YEP, FULLY VISIBLE
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LDA TMPL ; CLIP HEIGHT TO DST_HEIGHT
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CMP TMPL ; >= DST_HEIGHT
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BCS +
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LDA #$00 ; FULLY VISIBLE
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RTS
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+ LDA TMPL ; CLIP HEIGHT TO DST_HEIGHT
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;SEC
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SBC ESTKL-2,X
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STA ESTKL-4,X ; HEIGHT = DST_HEIGHT - Y
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VISY LDA #$00 ; FULLY VISIBLE
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CLC
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LDA #$00 ; VISIBLE WITH HEIGHT CLIP
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RTS
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; Y NEGATIVE, CHECK WITH H ADDED
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NEGY LDA ESTKL-2,X ; Y COORD
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@ -1547,15 +1551,15 @@ end
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export asm dcgrVLB#0
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PHP
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SEI
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STA $C079 ; Enable IOU access and reset VBL int on //c
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STA $C05B ; Enable VBL int
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STA $C079 ; Enable IOU access and reset VBL int on //c
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STA $C05B ; Enable VBL int
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- LDA $C019
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STA $C079 ; Reset VBL int on //c
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STA $C079 ; Reset VBL int on //c
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BMI -
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- LDA $C019
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BPL -
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STA $C05A ; Disable VBL int on //c
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STA $C078 ; Disable IOU access on //c
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STA $C05A ; Disable VBL int on //c
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STA $C078 ; Disable IOU access on //c
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PLP
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RTS
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end
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