2015-07-12 12:27:24 +00:00
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; PCE definitions. By Groepaz/Hitmem.
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2014-11-29 13:18:48 +00:00
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2015-08-29 13:58:57 +00:00
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; FIXME: optimize zeropage usage
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CURS_X = $30
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CURS_Y = $31
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SCREEN_PTR = $32 ;2
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CRAM_PTR = $34 ;2
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CHARCOLOR = $36
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RVS = $37
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BGCOLOR = $38
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tickcount = $39 ;4
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; FIXME: screen dimensions my change according to selected video mode
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screenrows = (224/8)
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charsperline = 61
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CH_HLINE = 1
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CH_VLINE = 2
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2014-11-29 13:18:48 +00:00
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; huc6270 - Video Display Controller (vdc)
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2015-08-29 13:58:57 +00:00
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VDC_MAWR = 0 ; Memory Address Write Register
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VDC_MARR = 1 ; Memory Address Read Register
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VDC_VWR = 2 ; VRAM Write Register
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VDC_VRR = 3 ; VRAM Read Register
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VDC_CR = 4 ; Control Register
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VDC_RCR = 5 ; Raster Counter Register
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VDC_BXR = 6 ; Background X-Scroll Register
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VDC_BYR = 7 ; Background Y-Scroll Register
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VDC_MWR = 8 ; Memory-access Width Register
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VDC_HSR = 9 ; Horizontal Sync Register (?)
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VDC_HDR = 10 ; Horizontal Display Register (?)
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VDC_VPR = 11 ; (unknown)
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VDC_VDW = 12 ; (unknown use)
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VDC_VCR = 13 ; (unknown use)
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VDC_DCR = 14 ; (DMA) Control Register
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VDC_SOUR = 15 ; (DMA) Source Register
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VDC_DESR = 16 ; (DMA) Destination Register
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VDC_LENR = 17 ; (DMA) Length Register
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VDC_SATB = 18 ; Sprite Attribute Table
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2014-11-29 13:18:48 +00:00
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2015-07-15 11:18:12 +00:00
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; VDC port
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; Note: absolute addressing mode must be used when writing to this port
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2015-07-12 12:27:24 +00:00
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VDC_CTRL = $0000
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VDC_DATA_LO = $0002
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VDC_DATA_HI = $0003
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2014-11-29 13:18:48 +00:00
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; huc6260 - Video Color Encoder (vce)
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; The DAC has a palette of 512 colours.
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; bitmap of the palette data is this: 0000000gggrrrbbb.
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; You can read and write the DAC-registers.
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2015-08-29 13:58:57 +00:00
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VCE = $0400 ; base
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2015-07-14 15:22:47 +00:00
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2015-08-29 13:58:57 +00:00
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VCE_CTRL = $0400 ; write$00 to reset
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VCE_ADDR_LO = $0402 ; LSB of byte offset into palette
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VCE_ADDR_HI = $0403 ; MSB of byte offset into palette
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VCE_DATA_LO = $0404 ; LSB of 16-bit palette data
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VCE_DATA_HI = $0405 ; MSB of 16-bit palette data
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2014-11-29 13:18:48 +00:00
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2015-07-14 15:22:47 +00:00
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; programmable sound generator (PSG)
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2015-08-29 13:58:57 +00:00
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PSG = $0800 ; base
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2015-07-14 15:22:47 +00:00
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; timer
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2015-08-29 13:58:57 +00:00
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TIMER = $0c00 ; base
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2015-07-14 15:22:47 +00:00
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2015-07-12 12:27:24 +00:00
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TIMER_COUNT = $0c00
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TIMER_CTRL = $0c01
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2014-11-29 13:18:48 +00:00
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2015-07-12 12:27:24 +00:00
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JOY_CTRL = $1000
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2014-11-29 13:18:48 +00:00
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2015-07-12 12:27:24 +00:00
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IRQ_MASK = $1402
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IRQ_STATUS = $1403
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2014-11-29 13:18:48 +00:00
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CDR_MEM_DISABLE = $1803
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2014-11-29 14:35:20 +00:00
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CDR_MEM_ENABLE = $1807
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2015-07-12 12:27:24 +00:00
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; Write VDC register
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.macro VREG arg1,arg2
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st0 #arg1
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st1 #<(arg2)
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st2 #>(arg2)
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.endmacro
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