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mirror of https://github.com/cc65/cc65.git synced 2026-01-22 17:16:21 +00:00
This commit is contained in:
mrdudz
2025-06-22 01:15:40 +02:00
parent c3b75f0ac1
commit 2ae30b5b50
2 changed files with 0 additions and 34 deletions

View File

@@ -680,39 +680,6 @@ void OH_BitBranch (const OpcDesc* D)
void OH_BitBranch_Q (const OpcDesc* D)
{
char* BranchLabel;
/* Get the operands */
unsigned char TestAddr = GetCodeByte (PC+3);
signed char BranchOffs = GetCodeByte (PC+4);
/* Calculate the target address for the branch */
unsigned BranchAddr = (((int) PC+5) + BranchOffs) & 0xFFFF;
/* Generate labels in pass 1. The bit branch codes are special in that
** they don't really match the remainder of the 6502 instruction set (they
** are a Rockwell addon), so we must pass additional flags as direct
** value to the second GenerateLabel call.
*/
GenerateLabel (D->Flags, TestAddr);
GenerateLabel (flLabel, BranchAddr);
/* Make a copy of an operand, so that
** the other operand can't overwrite it.
** [GetAddrArg() uses a statically-stored buffer.]
*/
BranchLabel = xstrdup (GetAddrArg (flLabel, BranchAddr));
/* Output the line */
OneLine (D, "%s,%s", GetAddrArg (D->Flags, TestAddr), BranchLabel);
xfree (BranchLabel);
}
void OH_BitBranch_m740 (const OpcDesc* D)
/* <bit> zp, rel
** NOTE: currently <bit> is part of the instruction

View File

@@ -108,7 +108,6 @@ void OH_Direct_Q (const OpcDesc*);
void OH_DirectIndirectZ_Q (const OpcDesc* D);
void OH_Absolute_Q (const OpcDesc* D);
void OH_AbsoluteX_Q (const OpcDesc* D);
void OH_BitBranch_Q (const OpcDesc* D);
void OH_DirectX_Q (const OpcDesc* D);
void OH_Implicit_ea_45GS02 (const OpcDesc* D);
void OH_Implicit_42_45GS02 (const OpcDesc* D);