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Don't empty the Receive Data Register on filling the Transmit Data Register 

The Receive Data Register and the Transmit Data Register share share a single address. Accessing that address with STA abs,X in order to fill the Transmit Data Register causes a 6502 false read which causes the Receive Data Register to be emptied.

The simplest way to work around that issue - which I chose here - is to move the base address for all ACIA accesses from page $C0 to page $BF. However, that adds an additional cycle to all read accesses. An alternative approach would be to only modify the single line `sta ACIA_DATA,x`.
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Oliver Schmidt 2022-09-08 17:11:30 +02:00 committed by GitHub
parent 253af1ed07
commit 5493c9e7c2
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1 changed files with 4 additions and 1 deletions
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libsrc/apple2/ser/a2.ssc.s
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@ -57,7 +57,9 @@
;----------------------------------------------------------------------------
; I/O definitions
ACIA = $C088
Offset = $8F ; Move 6502 false read out of I/O to page $BF
ACIA = $C088-Offset
ACIA_DATA = ACIA+0 ; Data register
ACIA_STATUS = ACIA+1 ; Status register
ACIA_CMD = ACIA+2 ; Command register
@ -197,6 +199,7 @@ SER_OPEN:
asl
asl
asl
adc Offset ; Assume carry to be clear
tax
; Check if the handshake setting is valid