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Don't empty the Receive Data Register on filling the Transmit Data Register
The Receive Data Register and the Transmit Data Register share share a single address. Accessing that address with STA abs,X in order to fill the Transmit Data Register causes a 6502 false read which causes the Receive Data Register to be emptied. The simplest way to work around that issue - which I chose here - is to move the base address for all ACIA accesses from page $C0 to page $BF. However, that adds an additional cycle to all read accesses. An alternative approach would be to only modify the single line `sta ACIA_DATA,x`.
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@ -57,7 +57,9 @@
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;----------------------------------------------------------------------------
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;----------------------------------------------------------------------------
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; I/O definitions
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; I/O definitions
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ACIA = $C088
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Offset = $8F ; Move 6502 false read out of I/O to page $BF
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ACIA = $C088-Offset
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ACIA_DATA = ACIA+0 ; Data register
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ACIA_DATA = ACIA+0 ; Data register
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ACIA_STATUS = ACIA+1 ; Status register
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ACIA_STATUS = ACIA+1 ; Status register
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ACIA_CMD = ACIA+2 ; Command register
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ACIA_CMD = ACIA+2 ; Command register
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@ -197,6 +199,7 @@ SER_OPEN:
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asl
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asl
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asl
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asl
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asl
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asl
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adc Offset ; Assume carry to be clear
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tax
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tax
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; Check if the handshake setting is valid
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; Check if the handshake setting is valid
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