mirror of
https://github.com/cc65/cc65.git
synced 2026-03-10 17:21:49 +00:00
original patch
This commit is contained in:
mrdudz
37
cfg/m740.cfg
Normal file
37
cfg/m740.cfg
Normal file
@@ -0,0 +1,37 @@
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FEATURES {
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STARTADDRESS: default = $8000;
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}
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SYMBOLS {
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__STACKSIZE__: type = weak, value = $0000; # 2k stack
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__STACKSTART__: type = weak, value = $100;
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__ZPSTART__: type = weak, value = $0000;
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}
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MEMORY {
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ZP: file = "", define = yes, start = __ZPSTART__, size = $001F;
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MAIN: file = %O, start = %S, size = __STACKSTART__ - __STACKSIZE__ - %S;
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}
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SEGMENTS {
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ZEROPAGE: load = ZP, type = zp;
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STARTUP: load = MAIN, type = ro, optional = yes;
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LOWCODE: load = MAIN, type = ro, optional = yes;
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ONCE: load = MAIN, type = ro, optional = yes;
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CODE: load = MAIN, type = rw;
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RODATA: load = MAIN, type = rw;
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DATA: load = MAIN, type = rw;
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BSS: load = MAIN, type = bss, define = yes;
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}
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FEATURES {
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CONDES: type = constructor,
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label = __CONSTRUCTOR_TABLE__,
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count = __CONSTRUCTOR_COUNT__,
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segment = ONCE;
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CONDES: type = destructor,
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label = __DESTRUCTOR_TABLE__,
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count = __DESTRUCTOR_COUNT__,
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segment = RODATA;
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CONDES: type = interruptor,
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label = __INTERRUPTOR_TABLE__,
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count = __INTERRUPTOR_COUNT__,
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segment = RODATA,
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import = __CALLIRQ__;
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}
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156
src/ca65/instr.c
156
src/ca65/instr.c
@@ -85,6 +85,12 @@ static void PutBlockTransfer (const InsDesc* Ins);
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static void PutBitBranch (const InsDesc* Ins);
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/* Handle 65C02 branch on bit condition */
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static void PutBitBranchm740 (const InsDesc* Ins);
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/* Handle m740 branch on bit condition */
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static void PutLDMm740 (const InsDesc* Ins);
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/* Handle m740 LDM instruction */
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static void PutREP (const InsDesc* Ins);
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/* Emit a REP instruction, track register sizes */
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@@ -1047,7 +1053,114 @@ static const struct {
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}
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};
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/* Instruction table for the m740 CPU */
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static const struct {
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unsigned Count;
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InsDesc Ins[97];
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} InsTabm740 = {
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sizeof (InsTabm740.Ins) / sizeof (InsTabm740.Ins[0]),
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{
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/* BEGIN SORTED.SH */
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{ "ADC", 0x080A26C, 0x60, 0, PutAll },
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{ "AND", 0x080A26C, 0x20, 0, PutAll },
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{ "ASL", 0x000006e, 0x02, 1, PutAll },
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{ "BBR0", 0x0000006, 0x13, 10, PutBitBranchm740 },
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{ "BBR1", 0x0000006, 0x33, 10, PutBitBranchm740 },
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{ "BBR2", 0x0000006, 0x53, 10, PutBitBranchm740 },
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{ "BBR3", 0x0000006, 0x73, 10, PutBitBranchm740 },
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{ "BBR4", 0x0000006, 0x93, 10, PutBitBranchm740 },
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{ "BBR5", 0x0000006, 0xb3, 10, PutBitBranchm740 },
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{ "BBR6", 0x0000006, 0xd3, 10, PutBitBranchm740 },
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{ "BBR7", 0x0000006, 0xf3, 10, PutBitBranchm740 },
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{ "BBS0", 0x0000006, 0x03, 10, PutBitBranchm740 },
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{ "BBS1", 0x0000006, 0x23, 10, PutBitBranchm740 },
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{ "BBS2", 0x0000006, 0x43, 10, PutBitBranchm740 },
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{ "BBS3", 0x0000006, 0x63, 10, PutBitBranchm740 },
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{ "BBS4", 0x0000006, 0x83, 10, PutBitBranchm740 },
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{ "BBS5", 0x0000006, 0xa3, 10, PutBitBranchm740 },
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{ "BBS6", 0x0000006, 0xc3, 10, PutBitBranchm740 },
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{ "BBS7", 0x0000006, 0xe3, 10, PutBitBranchm740 },
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{ "BCC", 0x0020000, 0x90, 0, PutPCRel8 },
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{ "BCS", 0x0020000, 0xb0, 0, PutPCRel8 },
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{ "BEQ", 0x0020000, 0xf0, 0, PutPCRel8 },
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{ "BIT", 0x000000C, 0x00, 2, PutAll },
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{ "BMI", 0x0020000, 0x30, 0, PutPCRel8 },
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{ "BNE", 0x0020000, 0xd0, 0, PutPCRel8 },
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{ "BPL", 0x0020000, 0x10, 0, PutPCRel8 },
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{ "BRA", 0x0020000, 0x80, 0, PutPCRel8 },
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{ "BRK", 0x0000001, 0x00, 0, PutAll },
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{ "BVC", 0x0020000, 0x50, 0, PutPCRel8 },
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{ "BVS", 0x0020000, 0x70, 0, PutPCRel8 },
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{ "CLC", 0x0000001, 0x18, 0, PutAll },
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{ "CLD", 0x0000001, 0xd8, 0, PutAll },
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{ "CLI", 0x0000001, 0x58, 0, PutAll },
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{ "CLT", 0x0000001, 0x12, 0, PutAll },
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{ "CLV", 0x0000001, 0xb8, 0, PutAll },
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{ "CMP", 0x080A26C, 0xc0, 0, PutAll },
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{ "COM", 0x0000004, 0x44, 1, PutAll },
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{ "CPX", 0x080000C, 0xe0, 1, PutAll },
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{ "CPY", 0x080000C, 0xc0, 1, PutAll },
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{ "DEC", 0x000006F, 0x00, 3, PutAll },
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{ "DEX", 0x0000001, 0xca, 0, PutAll },
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{ "DEY", 0x0000001, 0x88, 0, PutAll },
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{ "EOR", 0x080A26C, 0x40, 0, PutAll },
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{ "FST", 0x0000001, 0xe2, 0, PutAll },
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{ "INC", 0x000006f, 0x00, 4, PutAll },
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{ "INX", 0x0000001, 0xe8, 0, PutAll },
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{ "INY", 0x0000001, 0xc8, 0, PutAll },
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{ "JMP", 0x0000C08, 0x00, 12, PutAll },
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{ "JSR", 0x0080808, 0x00, 13, PutAll },
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{ "LDA", 0x080A26C, 0xa0, 0, PutAll },
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{ "LDM", 0x0000004, 0x3c, 6, PutLDMm740 },
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{ "LDX", 0x080030C, 0xa2, 1, PutAll },
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{ "LDY", 0x080006C, 0xa0, 1, PutAll },
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{ "LSR", 0x000006F, 0x42, 1, PutAll },
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{ "NOP", 0x0000001, 0xea, 0, PutAll },
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{ "ORA", 0x080A26C, 0x00, 0, PutAll },
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{ "PHA", 0x0000001, 0x48, 0, PutAll },
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{ "PHP", 0x0000001, 0x08, 0, PutAll },
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{ "PLA", 0x0000001, 0x68, 0, PutAll },
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{ "PLP", 0x0000001, 0x28, 0, PutAll },
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{ "RMB0", 0x0000006, 0x1b, 10, PutAll },
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{ "RMB1", 0x0000006, 0x3b, 10, PutAll },
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{ "RMB2", 0x0000006, 0x5b, 10, PutAll },
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{ "RMB3", 0x0000006, 0x7b, 10, PutAll },
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{ "RMB4", 0x0000006, 0x9b, 10, PutAll },
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{ "RMB5", 0x0000006, 0xbb, 10, PutAll },
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{ "RMB6", 0x0000006, 0xdb, 10, PutAll },
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{ "RMB7", 0x0000006, 0xfb, 10, PutAll },
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{ "ROL", 0x000006F, 0x22, 1, PutAll },
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{ "ROR", 0x000006F, 0x62, 1, PutAll },
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{ "RRF", 0x0000004, 0x82, 6, PutAll },
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{ "RTI", 0x0000001, 0x40, 0, PutAll },
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{ "RTS", 0x0000001, 0x60, 0, PutAll },
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{ "SBC", 0x080A26C, 0xe0, 0, PutAll },
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{ "SEC", 0x0000001, 0x38, 0, PutAll },
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{ "SED", 0x0000001, 0xf8, 0, PutAll },
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{ "SEI", 0x0000001, 0x78, 0, PutAll },
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{ "SET", 0x0000001, 0x32, 0, PutAll },
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{ "SLW", 0x0000001, 0xC2, 0, PutAll },
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{ "SMB0", 0x0000006, 0x0b, 10, PutAll },
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{ "SMB1", 0x0000006, 0x2b, 10, PutAll },
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{ "SMB2", 0x0000006, 0x4b, 10, PutAll },
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{ "SMB3", 0x0000006, 0x6b, 10, PutAll },
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{ "SMB4", 0x0000006, 0x8b, 10, PutAll },
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{ "SMB5", 0x0000006, 0xab, 10, PutAll },
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{ "SMB6", 0x0000006, 0xcb, 10, PutAll },
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{ "SMB7", 0x0000006, 0xeb, 10, PutAll },
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{ "STA", 0x000A26C, 0x80, 0, PutAll },
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{ "STP", 0x0000001, 0x42, 0, PutAll },
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{ "STX", 0x000010c, 0x82, 1, PutAll },
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{ "STY", 0x000002c, 0x80, 1, PutAll },
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{ "TAX", 0x0000001, 0xaa, 0, PutAll },
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{ "TAY", 0x0000001, 0xa8, 0, PutAll },
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{ "TSX", 0x0000001, 0xba, 0, PutAll },
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{ "TXA", 0x0000001, 0x8a, 0, PutAll },
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{ "TXS", 0x0000001, 0x9a, 0, PutAll },
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{ "TYA", 0x0000001, 0x98, 0, PutAll }
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/* END SORTED.SH */
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}
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};
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/* An array with instruction tables */
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static const InsTable* InsTabs[CPU_COUNT] = {
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@@ -1060,7 +1173,7 @@ static const InsTable* InsTabs[CPU_COUNT] = {
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(const InsTable*) &InsTab65816,
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(const InsTable*) &InsTabSweet16,
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(const InsTable*) &InsTabHuC6280,
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0, /* Mitsubishi 740 */
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(const InsTable*) &InsTabm740, /* Mitsubishi 740 */
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(const InsTable*) &InsTab4510,
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};
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const InsTable* InsTab = (const InsTable*) &InsTab6502;
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@@ -1068,7 +1181,7 @@ const InsTable* InsTab = (const InsTable*) &InsTab6502;
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/* Table to build the effective 65xx opcode from a base opcode and an
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** addressing mode. (The value in the table is ORed with the base opcode)
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*/
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static unsigned char EATab[12][AM65I_COUNT] = {
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static unsigned char EATab[14][AM65I_COUNT] = {
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{ /* Table 0 */
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0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
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0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
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@@ -1141,6 +1254,18 @@ static unsigned char EATab[12][AM65I_COUNT] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
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0x00, 0x00, 0x80, 0x00
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},
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{ /* Table 12 m740 JMP */
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0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0xb2, 0x6c, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 13 m740 JSR */
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0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00
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},
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};
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/* Table to build the effective SWEET16 opcode from a base opcode and an
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@@ -1361,6 +1486,12 @@ static void EmitCode (EffAddr* A)
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}
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static void PutLDMm740 (const InsDesc* Ins)
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{
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Emit0 (Ins->BaseCode);
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EmitWord (Expression ());
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}
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static long PutImmed8 (const InsDesc* Ins)
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/* Parse and emit an immediate 8 bit instruction. Return the value of the
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@@ -1481,6 +1612,22 @@ static void PutBitBranch (const InsDesc* Ins)
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EmitSigned (GenBranchExpr (1), 1);
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}
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static void PutBitBranchm740 (const InsDesc* Ins)
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/* Handle 65C02 branch on bit condition */
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{
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EffAddr A;
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/* HACK: hardcoded for zp addressing mode, this doesn't work all the time */
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A.AddrMode = 2;
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A.Opcode = Ins->BaseCode | EATab[Ins->ExtCode][A.AddrMode];
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/* Evaluate the addressing mode used */
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/* No error, output code */
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Emit0 (A.Opcode);
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EmitByte (Expression ());
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ConsumeComma ();
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EmitSigned (GenBranchExpr (1), 1);
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}
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||||
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||||
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static void PutREP (const InsDesc* Ins)
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@@ -1584,7 +1731,6 @@ static void PutTMAn (const InsDesc* Ins)
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** an immediate argument.
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*/
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{
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||||
/* Emit the TMA opcode itself */
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Emit0 (0x43);
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||||
/* Emit the argument, which is the opcode from the table */
|
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@@ -1640,10 +1786,8 @@ static void PutJMP (const InsDesc* Ins)
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*/
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{
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||||
EffAddr A;
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||||
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/* Evaluate the addressing mode used */
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if (EvalEA (Ins, &A)) {
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||||
|
||||
/* Check for indirect addressing */
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if ((A.AddrModeBit & AM65_ABS_IND) && (CPU < CPU_65SC02) && (RelaxChecks == 0)) {
|
||||
|
||||
|
||||
@@ -58,53 +58,60 @@
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||||
** When assembling for the 6502 or 65C02, all addressing modes that are not
|
||||
** available on these CPUs are removed before doing any checks.
|
||||
*/
|
||||
#define AM65_IMPLICIT 0x00000003UL
|
||||
#define AM65_ACCU 0x00000002UL
|
||||
#define AM65_DIR 0x00000004UL
|
||||
#define AM65_ABS 0x00000008UL
|
||||
#define AM65_ABS_LONG 0x00000010UL
|
||||
#define AM65_DIR_X 0x00000020UL
|
||||
#define AM65_ABS_X 0x00000040UL
|
||||
#define AM65_ABS_LONG_X 0x00000080UL
|
||||
#define AM65_DIR_Y 0x00000100UL
|
||||
#define AM65_ABS_Y 0x00000200UL
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||||
#define AM65_DIR_IND 0x00000400UL
|
||||
#define AM65_ABS_IND 0x00000800UL
|
||||
#define AM65_DIR_IND_LONG 0x00001000UL
|
||||
#define AM65_DIR_IND_Y 0x00002000UL
|
||||
#define AM65_DIR_IND_LONG_Y 0x00004000UL
|
||||
#define AM65_DIR_X_IND 0x00008000UL
|
||||
#define AM65_ABS_X_IND 0x00010000UL
|
||||
#define AM65_REL 0x00020000UL
|
||||
#define AM65_REL_LONG 0x00040000UL
|
||||
#define AM65_STACK_REL 0x00080000UL
|
||||
#define AM65_STACK_REL_IND_Y 0x00100000UL
|
||||
#define AM65_IMPLICIT 0x00000003UL /* IMP */
|
||||
#define AM65_ACCU 0x00000002UL /* A, BIT, A */
|
||||
#define AM65_DIR 0x00000004UL /* ZP, BIT, ZP */
|
||||
#define AM65_ABS 0x00000008UL /* ABS */
|
||||
#define AM65_ABS_LONG 0x00000010UL /* -- */
|
||||
#define AM65_DIR_X 0x00000020UL /* ZP,X */
|
||||
#define AM65_ABS_X 0x00000040UL /* ABS, X */
|
||||
#define AM65_ABS_LONG_X 0x00000080UL /* -- */
|
||||
#define AM65_DIR_Y 0x00000100UL /* ZP, Y */
|
||||
#define AM65_ABS_Y 0x00000200UL /* ABS, Y */
|
||||
#define AM65_DIR_IND 0x00000400UL /* ZP, IND */
|
||||
#define AM65_ABS_IND 0x00000800UL /* IND */
|
||||
#define AM65_DIR_IND_LONG 0x00001000UL /* -- */
|
||||
#define AM65_DIR_IND_Y 0x00002000UL /* IND, Y */
|
||||
#define AM65_DIR_IND_LONG_Y 0x00004000UL /* -- */
|
||||
#define AM65_DIR_X_IND 0x00008000UL /* IND, X */
|
||||
#define AM65_ABS_X_IND 0x00010000UL /* -- */
|
||||
#define AM65_REL 0x00020000UL /* REL */
|
||||
#define AM65_REL_LONG 0x00040000UL /* -- */
|
||||
#define AM65_STACK_REL 0x00080000UL /* SP ? */
|
||||
#define AM65_STACK_REL_IND_Y 0x00100000UL /* ? */
|
||||
#define AM65_IMM_ACCU 0x00200000UL
|
||||
#define AM65_IMM_INDEX 0x00400000UL
|
||||
#define AM65_IMM_IMPLICIT 0x00800000UL
|
||||
#define AM65_BLOCKMOVE 0x01000000UL
|
||||
#define AM65_BLOCKXFER 0x02000000UL
|
||||
#define AM65_ABS_IND_LONG 0x04000000UL
|
||||
#define AM65_IMM_IMPLICIT 0x00800000UL /* IMM */
|
||||
#define AM65_BLOCKMOVE 0x01000000UL /* -- */
|
||||
#define AM65_BLOCKXFER 0x02000000UL /* -- */
|
||||
#define AM65_ABS_IND_LONG 0x04000000UL /* -- */
|
||||
#define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */
|
||||
|
||||
/* Bitmask for all ZP operations that have correspondent ABS ops */
|
||||
/* $8524 */
|
||||
#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
|
||||
|
||||
/*$4 $20 $100 $400 $8000 */
|
||||
/* Bitmask for all ABS operations that have correspondent FAR ops */
|
||||
/* $48 */
|
||||
#define AM65_SET_ABS (AM65_ABS | AM65_ABS_X)
|
||||
|
||||
/* $8 $40 */
|
||||
/* Bitmask for all ZP operations */
|
||||
/* $8524 */
|
||||
#define AM65_ALL_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
|
||||
|
||||
/*$4 $20 $100 $400 $8000 */
|
||||
/* Bitmask for all ABS operations */
|
||||
/* $10a48 */
|
||||
#define AM65_ALL_ABS (AM65_ABS | AM65_ABS_X | AM65_ABS_Y | AM65_ABS_IND | AM65_ABS_X_IND)
|
||||
|
||||
/* $8 $40 $200 $800 $10000 */
|
||||
/* Bitmask for all FAR operations */
|
||||
/* $90 */
|
||||
#define AM65_ALL_FAR (AM65_ABS_LONG | AM65_ABS_LONG_X)
|
||||
/* $10 $80 */
|
||||
|
||||
/* Bitmask for all immediate operations */
|
||||
/* $8e00 000 */
|
||||
#define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD)
|
||||
|
||||
/* $200000 $400000 $800000 $8000000 */
|
||||
/* Bit numbers and count */
|
||||
#define AM65I_IMM_ACCU 21
|
||||
#define AM65I_IMM_INDEX 22
|
||||
|
||||
@@ -531,7 +531,22 @@ void OH_BitBranch (const OpcDesc* D)
|
||||
xfree (BranchLabel);
|
||||
}
|
||||
|
||||
void OH_BitBranchm740 (const OpcDesc* D)
|
||||
{
|
||||
unsigned Bit = GetCodeByte (PC) >> 5;
|
||||
unsigned Addr = GetCodeByte (PC+1);
|
||||
signed char BranchOffs = GetCodeByte (PC+2);
|
||||
|
||||
/* Calculate the target address for the branch */
|
||||
unsigned BranchAddr = (((int) PC+3) + BranchOffs) & 0xFFFF;
|
||||
|
||||
/* Generate a label in pass 1 */
|
||||
GenerateLabel (D->Flags, Addr);
|
||||
GenerateLabel (flLabel, BranchAddr);
|
||||
|
||||
/* Output the line */
|
||||
OneLine (D, "%01X,%s,%s", Bit, GetAddrArg (D->Flags, Addr), GetAddrArg (flLabel, BranchAddr));
|
||||
}
|
||||
|
||||
void OH_ImmediateDirect (const OpcDesc* D)
|
||||
{
|
||||
|
||||
@@ -78,6 +78,7 @@ void OH_DirectXIndirect (const OpcDesc*);
|
||||
void OH_AbsoluteIndirect (const OpcDesc*);
|
||||
|
||||
void OH_BitBranch (const OpcDesc*);
|
||||
void OH_BitBranchm740 (const OpcDesc*);
|
||||
|
||||
void OH_ImmediateDirect (const OpcDesc*);
|
||||
void OH_ImmediateDirectX (const OpcDesc*);
|
||||
|
||||
@@ -55,7 +55,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $04 */
|
||||
{ "ora", 2, flUseLabel, OH_Direct }, /* $05 */
|
||||
{ "asl", 2, flUseLabel, OH_Direct }, /* $06 */
|
||||
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $07 */
|
||||
{ "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $07 */
|
||||
{ "php", 1, flNone, OH_Implicit }, /* $08 */
|
||||
{ "ora", 2, flNone, OH_Immediate }, /* $09 */
|
||||
{ "asl", 1, flNone, OH_Accumulator }, /* $0a */
|
||||
@@ -71,7 +71,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $14 */
|
||||
{ "ora", 2, flUseLabel, OH_DirectX }, /* $15 */
|
||||
{ "asl", 2, flUseLabel, OH_DirectX }, /* $16 */
|
||||
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $17 */
|
||||
{ "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $17 */
|
||||
{ "clc", 1, flNone, OH_Implicit }, /* $18 */
|
||||
{ "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */
|
||||
{ "dec", 1, flNone, OH_Accumulator }, /* $1a */
|
||||
@@ -87,7 +87,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "bit", 2, flUseLabel, OH_Direct }, /* $24 */
|
||||
{ "and", 2, flUseLabel, OH_Direct }, /* $25 */
|
||||
{ "rol", 2, flUseLabel, OH_Direct }, /* $26 */
|
||||
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $27 */
|
||||
{ "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $27 */
|
||||
{ "plp", 1, flNone, OH_Implicit }, /* $28 */
|
||||
{ "and", 2, flNone, OH_Immediate }, /* $29 */
|
||||
{ "rol", 1, flNone, OH_Accumulator }, /* $2a */
|
||||
@@ -103,7 +103,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $34 */
|
||||
{ "and", 2, flUseLabel, OH_DirectX }, /* $35 */
|
||||
{ "rol", 2, flUseLabel, OH_DirectX }, /* $36 */
|
||||
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $37 */
|
||||
{ "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $37 */
|
||||
{ "sec", 1, flNone, OH_Implicit }, /* $38 */
|
||||
{ "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */
|
||||
{ "inc", 1, flNone, OH_Accumulator }, /* $3a */
|
||||
@@ -119,7 +119,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "com", 2, flUseLabel, OH_Direct }, /* $44 */
|
||||
{ "eor", 2, flUseLabel, OH_Direct }, /* $45 */
|
||||
{ "lsr", 2, flUseLabel, OH_Direct }, /* $46 */
|
||||
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $47 */
|
||||
{ "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $47 */
|
||||
{ "pha", 1, flNone, OH_Implicit }, /* $48 */
|
||||
{ "eor", 2, flNone, OH_Immediate }, /* $49 */
|
||||
{ "lsr", 1, flNone, OH_Accumulator }, /* $4a */
|
||||
@@ -135,7 +135,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $54 */
|
||||
{ "eor", 2, flUseLabel, OH_DirectX }, /* $55 */
|
||||
{ "lsr", 2, flUseLabel, OH_DirectX }, /* $56 */
|
||||
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $57 */
|
||||
{ "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $57 */
|
||||
{ "cli", 1, flNone, OH_Implicit }, /* $58 */
|
||||
{ "eor", 3, flUseLabel, OH_AbsoluteY }, /* $59 */
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $5a */
|
||||
@@ -151,7 +151,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "tst", 2, flUseLabel, OH_Direct }, /* $64 */
|
||||
{ "adc", 2, flUseLabel, OH_Direct }, /* $65 */
|
||||
{ "ror", 2, flUseLabel, OH_Direct }, /* $66 */
|
||||
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $67 */
|
||||
{ "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $67 */
|
||||
{ "pla", 1, flNone, OH_Implicit }, /* $68 */
|
||||
{ "adc", 2, flNone, OH_Immediate }, /* $69 */
|
||||
{ "ror", 1, flNone, OH_Accumulator }, /* $6a */
|
||||
@@ -167,7 +167,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $74 */
|
||||
{ "adc", 2, flUseLabel, OH_DirectX }, /* $75 */
|
||||
{ "ror", 2, flUseLabel, OH_DirectX }, /* $76 */
|
||||
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $77 */
|
||||
{ "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $77 */
|
||||
{ "sei", 1, flNone, OH_Implicit }, /* $78 */
|
||||
{ "adc", 3, flUseLabel, OH_AbsoluteY }, /* $79 */
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $7a */
|
||||
@@ -183,7 +183,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "sty", 2, flUseLabel, OH_Direct }, /* $84 */
|
||||
{ "sta", 2, flUseLabel, OH_Direct }, /* $85 */
|
||||
{ "stx", 2, flUseLabel, OH_Direct }, /* $86 */
|
||||
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $87 */
|
||||
{ "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $87 */
|
||||
{ "dey", 1, flNone, OH_Implicit }, /* $88 */
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $89 */
|
||||
{ "txa", 1, flNone, OH_Implicit }, /* $8a */
|
||||
@@ -199,7 +199,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "sty", 2, flUseLabel, OH_DirectX }, /* $94 */
|
||||
{ "sta", 2, flUseLabel, OH_DirectX }, /* $95 */
|
||||
{ "stx", 2, flUseLabel, OH_DirectY }, /* $96 */
|
||||
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $97 */
|
||||
{ "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $97 */
|
||||
{ "tya", 1, flNone, OH_Implicit }, /* $98 */
|
||||
{ "sta", 3, flUseLabel, OH_AbsoluteY }, /* $99 */
|
||||
{ "txs", 1, flNone, OH_Implicit }, /* $9a */
|
||||
@@ -215,7 +215,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "ldy", 2, flUseLabel, OH_Direct }, /* $a4 */
|
||||
{ "lda", 2, flUseLabel, OH_Direct }, /* $a5 */
|
||||
{ "ldx", 2, flUseLabel, OH_Direct }, /* $a6 */
|
||||
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $a7 */
|
||||
{ "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $a7 */
|
||||
{ "tay", 1, flNone, OH_Implicit }, /* $a8 */
|
||||
{ "lda", 2, flNone, OH_Immediate }, /* $a9 */
|
||||
{ "tax", 1, flNone, OH_Implicit }, /* $aa */
|
||||
@@ -231,7 +231,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "ldy", 2, flUseLabel, OH_DirectX }, /* $b4 */
|
||||
{ "lda", 2, flUseLabel, OH_DirectX }, /* $b5 */
|
||||
{ "ldx", 2, flUseLabel, OH_DirectY }, /* $b6 */
|
||||
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $b7 */
|
||||
{ "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $b7 */
|
||||
{ "clv", 1, flNone, OH_Implicit }, /* $b8 */
|
||||
{ "lda", 3, flUseLabel, OH_AbsoluteY }, /* $b9 */
|
||||
{ "tsx", 1, flNone, OH_Implicit }, /* $ba */
|
||||
@@ -247,7 +247,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "cpy", 2, flUseLabel, OH_Direct }, /* $c4 */
|
||||
{ "cmp", 2, flUseLabel, OH_Direct }, /* $c5 */
|
||||
{ "dec", 2, flUseLabel, OH_Direct }, /* $c6 */
|
||||
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $c7 */
|
||||
{ "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $c7 */
|
||||
{ "iny", 1, flNone, OH_Implicit }, /* $c8 */
|
||||
{ "cmp", 2, flNone, OH_Immediate }, /* $c9 */
|
||||
{ "dex", 1, flNone, OH_Implicit }, /* $ca */
|
||||
@@ -263,7 +263,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $d4 */
|
||||
{ "cmp", 2, flUseLabel, OH_DirectX }, /* $d5 */
|
||||
{ "dec", 2, flUseLabel, OH_DirectX }, /* $d6 */
|
||||
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $d7 */
|
||||
{ "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $d7 */
|
||||
{ "cld", 1, flNone, OH_Implicit }, /* $d8 */
|
||||
{ "cmp", 3, flUseLabel, OH_AbsoluteY }, /* $d9 */
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $da */
|
||||
@@ -279,7 +279,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "cpx", 2, flUseLabel, OH_Direct }, /* $e4 */
|
||||
{ "sbc", 2, flUseLabel, OH_Direct }, /* $e5 */
|
||||
{ "inc", 2, flUseLabel, OH_Direct }, /* $e6 */
|
||||
{ "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $e7 */
|
||||
{ "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $e7 */
|
||||
{ "inx", 1, flNone, OH_Implicit }, /* $e8 */
|
||||
{ "sbc", 2, flNone, OH_Immediate }, /* $e9 */
|
||||
{ "nop", 1, flNone, OH_Implicit }, /* $ea */
|
||||
@@ -295,7 +295,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $f4 */
|
||||
{ "sbc", 2, flUseLabel, OH_DirectX }, /* $f5 */
|
||||
{ "inc", 2, flUseLabel, OH_DirectX }, /* $f6 */
|
||||
{ "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $f7 */
|
||||
{ "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $f7 */
|
||||
{ "sed", 1, flNone, OH_Implicit }, /* $f8 */
|
||||
{ "sbc", 3, flUseLabel, OH_AbsoluteY }, /* $f9 */
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $fa */
|
||||
|
||||
Reference in New Issue
Block a user