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Changed naming absvaludiv -> absvaludiv16.

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This commit is contained in:
IrgendwerA8 2018-05-24 11:31:43 +02:00
parent dd411efd1c
commit 9c1cb0801c
3 changed files with 8 additions and 8 deletions
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4
libsrc/runtime/absvaludiv.s
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@ -6,12 +6,12 @@
; When negating values, we will ignore the possibility here, that one of the
; values is $8000, in which case the negate will fail.
.export absvaludiv
.export absvaludiv16
.import _abs, popax, udiv16
.importzp ptr1, ptr4
absvaludiv:
absvaludiv16:
jsr _abs
sta ptr4
stx ptr4+1 ; Save right absolute operand

6
libsrc/runtime/div.s
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@ -8,7 +8,7 @@
; values is $8000, in which case the negate will fail.
.export tosdiva0, tosdivax
.import absvaludiv, negax
.import absvaludiv16, negax
.importzp sp, ptr1, tmp1
tosdiva0:
@ -20,10 +20,10 @@ tosdivax:
eor (sp),y ; eor with lhs high byte
sta tmp1 ; save post negation indicator to tmp1
pla ; back to entry accu
jsr absvaludiv
jsr absvaludiv16
ldx ptr1+1
lda ptr1
ldy tmp1 ; fetch idicator
ldy tmp1 ; fetch indicator
bmi negate
rts
negate: jmp negax

6
libsrc/runtime/mod.s
View File

@ -8,7 +8,7 @@
; values is $8000, in which case the negate will fail.
.export tosmoda0, tosmodax
.import absvaludiv, negax
.import absvaludiv16, negax
.importzp sp, sreg, tmp1
tosmoda0:
@ -23,10 +23,10 @@ tosmodax:
lda (sp),y
sta tmp1 ; save post negation indicator to tmp1
pla ; back to entry accu
jsr absvaludiv
jsr absvaludiv16
ldx sreg+1 ; remainder to return registers
lda sreg
ldy tmp1 ; fetch idicator
ldy tmp1 ; fetch indicator
bmi negate
rts
negate: jmp negax