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09495519c0
The configuration file and runtime (crt0.s) provided for the default NES
ROM layout (2x16k PRG, 8k CHR) incorrectly added interrupts (IRQ1, IRQ2,
TIMERIRQ) which are not supported by the NES hardware. For example, see
the NESdev wiki, which makes no reference to these interrupts.
https://wiki.nesdev.com/w/index.php/CPU_memory_map
The VECTORS region was also incorrectly set to 0xFFF6, which would have
left the 0xFFF4 normally unspecified. This did not result in any error,
however, since cc65 simply placed ROMV directly after ROM0 regardless of
start address.
(This layout may be due to a copy-and-paste from the PC-Engine
configuration, whose interrupt registers start at 0xFFF6, begins with
the three interrupts listed above, followed by NMI and START, and does
not end with a final IRQ interrupt.)
Despite the absence of any actual error, since START is still placed at
0xFFFC, this patch removes the nonexistent interrupts and also correctly
aligns the ROM0 and ROMV regions. It also has the (admittedly very
minor) benefit of freeing up 6 additional bytes for ROM0.
63 lines
2.1 KiB
INI
63 lines
2.1 KiB
INI
SYMBOLS {
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__STACKSIZE__: type = weak, value = $0300; # 3 pages stack
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}
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MEMORY {
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ZP: file = "", start = $0002, size = $001A, type = rw, define = yes;
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# INES Cartridge Header
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HEADER: file = %O, start = $0000, size = $0010, fill = yes;
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# 2 16K ROM Banks
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# - startup
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# - code
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# - rodata
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# - data (load)
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ROM0: file = %O, start = $8000, size = $7FFA, fill = yes, define = yes;
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# Hardware Vectors at End of 2nd 8K ROM
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ROMV: file = %O, start = $FFFA, size = $0006, fill = yes;
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# 1 8k CHR Bank
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ROM2: file = %O, start = $0000, size = $2000, fill = yes;
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# standard 2k SRAM (-zeropage)
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# $0100-$0200 cpu stack
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# $0200-$0500 3 pages for ppu memory write buffer
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# $0500-$0800 3 pages for cc65 parameter stack
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SRAM: file = "", start = $0500, size = __STACKSIZE__, define = yes;
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# additional 8K SRAM Bank
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# - data (run)
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# - bss
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# - heap
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RAM: file = "", start = $6000, size = $2000, define = yes;
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}
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SEGMENTS {
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ZEROPAGE: load = ZP, type = zp;
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HEADER: load = HEADER, type = ro;
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STARTUP: load = ROM0, type = ro, define = yes;
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LOWCODE: load = ROM0, type = ro, optional = yes;
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ONCE: load = ROM0, type = ro, optional = yes;
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CODE: load = ROM0, type = ro, define = yes;
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RODATA: load = ROM0, type = ro, define = yes;
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DATA: load = ROM0, run = RAM, type = rw, define = yes;
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VECTORS: load = ROMV, type = rw;
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CHARS: load = ROM2, type = rw;
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BSS: load = RAM, type = bss, define = yes;
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}
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FEATURES {
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CONDES: type = constructor,
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label = __CONSTRUCTOR_TABLE__,
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count = __CONSTRUCTOR_COUNT__,
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segment = ONCE;
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CONDES: type = destructor,
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label = __DESTRUCTOR_TABLE__,
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count = __DESTRUCTOR_COUNT__,
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segment = RODATA;
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CONDES: type = interruptor,
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label = __INTERRUPTOR_TABLE__,
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count = __INTERRUPTOR_COUNT__,
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segment = RODATA,
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import = __CALLIRQ__;
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}
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