Oliver Schmidt 5493c9e7c2 Don't empty the Receive Data Register on filling the Transmit Data Register ... The Receive Data Register and the Transmit Data Register share share a single address. Accessing that address with STA abs,X in order to fill the Transmit Data Register causes a 6502 false read which causes the Receive Data Register to be emptied. The simplest way to work around that issue - which I chose here - is to move the base address for all ACIA accesses from page $C0 to page $BF. However, that adds an additional cycle to all read accesses. An alternative approach would be to only modify the single line `sta ACIA_DATA,x`.		2022-09-08 17:11:30 +02:00
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a2.ssc.s	Don't empty the Receive Data Register on filling the Transmit Data Register	2022-09-08 17:11:30 +02:00