mirror of https://github.com/ariejan/i6502.git
Initial commit of the i6502 emulator.
This commit is contained in:
Ariejan de Vroom
commit
4a155cad33
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@ -0,0 +1,5 @@
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# RAM memory dumps
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core
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# Binary
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i6502
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@ -0,0 +1,100 @@
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// Package bus represents the 16-bit address and 8-bit data bus for the
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// 6502. Different memory modules can be used for different addresses.
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package bus
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import (
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"fmt"
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"github.com/ariejan/i6502/memory"
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)
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type busModule struct {
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memory memory.Memory
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name string
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start uint16
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end uint16
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}
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// A 16-bit address and 8-bit data bus. It maps access to different
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// attached modules, like Ram or Rom.
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type Bus struct {
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modules []busModule
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}
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func (module busModule) String() string {
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return fmt.Sprintf("%s\t0x%04X-%04X\n", module.name, module.start, module.end)
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}
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func (bus *Bus) String() string {
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output := "\n\nAddress bus modules:\n\n"
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for _, module := range bus.modules {
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// output = append(output, module.String())
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output += module.String()
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}
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return output
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}
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// Creates a new Bus, no modules are attached by default.
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func CreateBus() (*Bus, error) {
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return &Bus{modules: make([]busModule, 0)}, nil
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}
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func (bus *Bus) Attach(memory memory.Memory, name string, offset uint16) error {
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offsetMemory := OffsetMemory{Offset: offset, Memory: memory}
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end := offset + uint16(memory.Size()-1)
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module := busModule{memory: offsetMemory, name: name, start: offset, end: end}
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bus.modules = append(bus.modules, module)
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return nil
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}
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func (bus *Bus) backendFor(address uint16) (memory.Memory, error) {
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for _, module := range bus.modules {
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if address >= module.start && address <= module.end {
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return module.memory, nil
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}
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}
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return nil, fmt.Errorf("No module addressable at 0x%04X", address)
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}
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// Read an 8-bit value from the module mapped on the bus at the
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// given 16-bit address.
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func (bus *Bus) Read(address uint16) byte {
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memory, err := bus.backendFor(address)
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if err != nil {
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panic(err)
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}
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value := memory.Read(address)
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return value
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}
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// Write an 8-bit value to the module mapped on the bus through the
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// 16-bit address.
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func (bus *Bus) Write(address uint16, value byte) {
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memory, err := bus.backendFor(address)
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if err != nil {
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panic(err)
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}
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memory.Write(address, value)
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}
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// Helper method to read a 16-bit value from
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// Note: LSB goes first: address [lo] + address+1 [hi]
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func (bus *Bus) Read16(address uint16) uint16 {
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lo := uint16(bus.Read(address))
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hi := uint16(bus.Read(address + 1))
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return hi<<8 | lo
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}
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// Helper to write a 16-bit value to address and address + 1
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// Note: LSB goes first: address [lo] + address+1 [hi]
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func (bus *Bus) Write16(address uint16, value uint16) {
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bus.Write(address, byte(value))
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bus.Write(address+1, byte(value>>8))
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}
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@ -0,0 +1,20 @@
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package bus
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import (
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"github.com/ariejan/i6502/memory"
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)
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// The AddressDecoder routes a full 16-bit address to the
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// appropriate relatie Memory component address.
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type OffsetMemory struct {
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Offset uint16
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memory.Memory
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}
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func (offsetMemory OffsetMemory) Read(address uint16) byte {
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return offsetMemory.Memory.Read(address - offsetMemory.Offset)
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}
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func (offsetMemory OffsetMemory) Write(address uint16, value byte) {
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offsetMemory.Memory.Write(address-offsetMemory.Offset, value)
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}
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@ -0,0 +1,634 @@
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package cpu
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import (
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"fmt"
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"github.com/ariejan/i6502/bus"
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"strings"
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)
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// Status register flags
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const (
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sCarry = iota
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sZero
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sInterrupt
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sDecimal
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sBreak
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_
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sOverflow
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sNegative
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)
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// Beginning of the stack.
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// The stack grows downward, so it starts at 0x1FF
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const StackBase = 0x0100
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type Cpu struct {
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// Program counter
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PC uint16
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// Accumulator
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A byte
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// X, Y general purpose/index registers
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X byte
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Y byte
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// Stack pointer
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SP byte
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// Status registers
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SR byte
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// Memory bus
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Bus *bus.Bus
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// Handle exiting
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ExitChan chan int
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}
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// Reset the CPU, identical to triggering the RESB pin.
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// This resets the status register and loads the _reset vector_ from
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// address 0xFFFC into the Program Counter. Note this is a 16 bit value, read from
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// 0xFFFC-FFFD
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func (c *Cpu) Reset() {
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c.PC = c.Bus.Read16(0xFFFC)
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c.SR = 0x34
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}
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func (c *Cpu) String() string {
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return fmt.Sprintf(
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"CPU PC:0x%04X A:0x%02X X:0x%02X Y:0x%02X SP:0x%02X SR:%s",
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c.PC, c.A, c.X, c.Y, c.SP,
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c.statusString(),
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)
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}
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func (c *Cpu) Step() {
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// Read the instruction (including operands)
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instruction := ReadInstruction(c.PC, c.Bus)
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// Move the Program Counter forward, depending
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// on the size of the optype we just read.
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c.PC += uint16(instruction.Bytes)
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// Execute the instruction
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c.execute(instruction)
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}
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func (c *Cpu) stackHead(offset int8) uint16 {
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return uint16(StackBase) + uint16(c.SP) + uint16(offset)
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}
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func (c *Cpu) resolveOperand(in Instruction) uint8 {
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switch in.addressing {
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case immediate:
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return in.Op8
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default:
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return c.Bus.Read(c.memoryAddress(in))
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}
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}
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func (c *Cpu) memoryAddress(in Instruction) uint16 {
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switch in.addressing {
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case absolute:
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return in.Op16
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case absoluteX:
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return in.Op16 + uint16(c.X)
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case absoluteY:
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return in.Op16 + uint16(c.Y)
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// Indexed Indirect (X)
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// Operand is the zero-page location of a little-endian 16-bit base address.
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// The X register is added (wrapping; discarding overflow) before loading.
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// The resulting address loaded from (base+X) becomes the effective operand.
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// (base + X) must be in zero-page.
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case indirectX:
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location := uint16(in.Op8 + c.X)
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if location == 0xFF {
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panic("Indexed indirect high-byte not on zero page.")
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}
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return c.Bus.Read16(location)
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// Indirect Indexed (Y)
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// Operand is the zero-page location of a little-endian 16-bit address.
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// The address is loaded, and then the Y register is added to it.
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// The resulting loaded_address + Y becomes the effective operand.
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case indirectY:
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return c.Bus.Read16(uint16(in.Op8)) + uint16(c.Y)
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case zeropage:
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return uint16(in.Op8)
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case zeropageX:
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return uint16(in.Op8 + c.X)
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case zeropageY:
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return uint16(in.Op8 + c.Y)
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default:
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panic("unhandled addressing")
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}
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}
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func (c *Cpu) getStatus(bit uint8) bool {
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return c.getStatusInt(bit) == 1
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}
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func (c *Cpu) getStatusInt(bit uint8) uint8 {
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return (c.SR >> bit) & 1
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}
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func (c *Cpu) setStatus(bit uint8, state bool) {
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if state {
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c.SR |= 1 << bit
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} else {
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c.SR &^= 1 << bit
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}
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}
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func (c *Cpu) updateStatus(value uint8) {
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c.setStatus(sZero, value == 0)
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c.setStatus(sNegative, (value>>7) == 1)
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}
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func (c *Cpu) statusString() string {
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chars := "nv_bdizc"
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out := make([]string, 8)
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for i := 0; i < 8; i++ {
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if c.getStatus(uint8(7 - i)) {
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out[i] = string(chars[i])
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} else {
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out[i] = "-"
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}
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}
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return strings.Join(out, "")
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}
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func (c *Cpu) branch(in Instruction) {
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relative := int8(in.Op8) // signed
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if relative >= 0 {
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c.PC += uint16(relative)
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} else {
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c.PC -= uint16(-relative)
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}
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}
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func (c *Cpu) execute(in Instruction) {
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switch in.id {
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case adc:
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c.ADC(in)
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case and:
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c.AND(in)
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case asl:
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c.ASL(in)
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case bcc:
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c.BCC(in)
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case bcs:
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c.BCS(in)
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case beq:
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c.BEQ(in)
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case bmi:
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c.BMI(in)
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case bne:
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c.BNE(in)
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case bpl:
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c.BPL(in)
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case brk:
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c.BRK(in)
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case clc:
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c.CLC(in)
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case cld:
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c.CLD(in)
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case cli:
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c.CLI(in)
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case cmp:
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c.CMP(in)
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case cpx:
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c.CPX(in)
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case cpy:
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c.CPY(in)
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case dec:
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c.DEC(in)
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case dex:
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c.DEX(in)
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case dey:
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c.DEY(in)
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case eor:
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c.EOR(in)
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case inc:
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c.INC(in)
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case inx:
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c.INX(in)
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case iny:
|
||||
c.INY(in)
|
||||
case jmp:
|
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c.JMP(in)
|
||||
case jsr:
|
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c.JSR(in)
|
||||
case lda:
|
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c.LDA(in)
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case ldx:
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c.LDX(in)
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||||
case ldy:
|
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c.LDY(in)
|
||||
case lsr:
|
||||
c.LSR(in)
|
||||
case nop:
|
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c.NOP(in)
|
||||
case ora:
|
||||
c.ORA(in)
|
||||
case pha:
|
||||
c.PHA(in)
|
||||
case pla:
|
||||
c.PLA(in)
|
||||
case rol:
|
||||
c.ROL(in)
|
||||
case ror:
|
||||
c.ROR(in)
|
||||
case rts:
|
||||
c.RTS(in)
|
||||
case sbc:
|
||||
c.SBC(in)
|
||||
case sec:
|
||||
c.SEC(in)
|
||||
case sei:
|
||||
c.SEI(in)
|
||||
case sta:
|
||||
c.STA(in)
|
||||
case stx:
|
||||
c.STX(in)
|
||||
case sty:
|
||||
c.STY(in)
|
||||
case tax:
|
||||
c.TAX(in)
|
||||
case tay:
|
||||
c.TAY(in)
|
||||
case tsx:
|
||||
c.TSX(in)
|
||||
case txa:
|
||||
c.TXA(in)
|
||||
case txs:
|
||||
c.TXS(in)
|
||||
case tya:
|
||||
c.TYA(in)
|
||||
case _end:
|
||||
c._END(in)
|
||||
default:
|
||||
panic(fmt.Sprintf("Unhandled instruction: %v", in))
|
||||
}
|
||||
}
|
||||
|
||||
// ADC: Add memory and carry to accumulator.
|
||||
func (c *Cpu) ADC(in Instruction) {
|
||||
value16 := uint16(c.A) + uint16(c.resolveOperand(in)) + uint16(c.getStatusInt(sCarry))
|
||||
c.setStatus(sCarry, value16 > 0xFF)
|
||||
c.A = uint8(value16)
|
||||
c.updateStatus(c.A)
|
||||
}
|
||||
|
||||
// AND: And accumulator with memory.
|
||||
func (c *Cpu) AND(in Instruction) {
|
||||
c.A &= c.resolveOperand(in)
|
||||
c.updateStatus(c.A)
|
||||
}
|
||||
|
||||
// ASL: Shift memory or accumulator left one bit.
|
||||
func (c *Cpu) ASL(in Instruction) {
|
||||
switch in.addressing {
|
||||
case accumulator:
|
||||
c.setStatus(sCarry, (c.A>>7) == 1) // carry = old bit 7
|
||||
c.A <<= 1
|
||||
c.updateStatus(c.A)
|
||||
default:
|
||||
address := c.memoryAddress(in)
|
||||
value := c.Bus.Read(address)
|
||||
c.setStatus(sCarry, (value>>7) == 1) // carry = old bit 7
|
||||
value <<= 1
|
||||
c.Bus.Write(address, value)
|
||||
c.updateStatus(value)
|
||||
}
|
||||
}
|
||||
|
||||
// BCC: Branch if carry clear.
|
||||
func (c *Cpu) BCC(in Instruction) {
|
||||
if !c.getStatus(sCarry) {
|
||||
c.branch(in)
|
||||
}
|
||||
}
|
||||
|
||||
// BCS: Branch if carry set.
|
||||
func (c *Cpu) BCS(in Instruction) {
|
||||
if c.getStatus(sCarry) {
|
||||
c.branch(in)
|
||||
}
|
||||
}
|
||||
|
||||
// BEQ: Branch if equal (z=1).
|
||||
func (c *Cpu) BEQ(in Instruction) {
|
||||
if c.getStatus(sZero) {
|
||||
c.branch(in)
|
||||
}
|
||||
}
|
||||
|
||||
// BMI: Branch if negative.
|
||||
func (c *Cpu) BMI(in Instruction) {
|
||||
if c.getStatus(sNegative) {
|
||||
c.branch(in)
|
||||
}
|
||||
}
|
||||
|
||||
// BNE: Branch if not equal.
|
||||
func (c *Cpu) BNE(in Instruction) {
|
||||
if !c.getStatus(sZero) {
|
||||
c.branch(in)
|
||||
}
|
||||
}
|
||||
|
||||
// BPL: Branch if positive.
|
||||
func (c *Cpu) BPL(in Instruction) {
|
||||
if !c.getStatus(sNegative) {
|
||||
c.branch(in)
|
||||
}
|
||||
}
|
||||
|
||||
// BRK: software interrupt
|
||||
func (c *Cpu) BRK(in Instruction) {
|
||||
// temporarily used to dump status
|
||||
fmt.Println("BRK:", c)
|
||||
}
|
||||
|
||||
// CLC: Clear carry flag.
|
||||
func (c *Cpu) CLC(in Instruction) {
|
||||
c.setStatus(sCarry, false)
|
||||
}
|
||||
|
||||
// CLD: Clear decimal mode flag.
|
||||
func (c *Cpu) CLD(in Instruction) {
|
||||
c.setStatus(sDecimal, false)
|
||||
}
|
||||
|
||||
// CLI: Clear interrupt-disable flag.
|
||||
func (c *Cpu) CLI(in Instruction) {
|
||||
c.setStatus(sInterrupt, true)
|
||||
}
|
||||
|
||||
// CMP: Compare accumulator with memory.
|
||||
func (c *Cpu) CMP(in Instruction) {
|
||||
value := c.resolveOperand(in)
|
||||
c.setStatus(sCarry, c.A >= value)
|
||||
c.updateStatus(c.A - value)
|
||||
}
|
||||
|
||||
// CPX: Compare index register X with memory.
|
||||
func (c *Cpu) CPX(in Instruction) {
|
||||
value := c.resolveOperand(in)
|
||||
c.setStatus(sCarry, c.X >= value)
|
||||
c.updateStatus(c.X - value)
|
||||
}
|
||||
|
||||
// CPY: Compare index register Y with memory.
|
||||
func (c *Cpu) CPY(in Instruction) {
|
||||
value := c.resolveOperand(in)
|
||||
c.setStatus(sCarry, c.Y >= value)
|
||||
c.updateStatus(c.Y - value)
|
||||
}
|
||||
|
||||
// DEC: Decrement.
|
||||
func (c *Cpu) DEC(in Instruction) {
|
||||
address := c.memoryAddress(in)
|
||||
value := c.Bus.Read(address) - 1
|
||||
c.Bus.Write(address, value)
|
||||
c.updateStatus(value)
|
||||
}
|
||||
|
||||
// DEX: Decrement index register X.
|
||||
func (c *Cpu) DEX(in Instruction) {
|
||||
c.X--
|
||||
c.updateStatus(c.X)
|
||||
}
|
||||
|
||||
// DEY: Decrement index register Y.
|
||||
func (c *Cpu) DEY(in Instruction) {
|
||||
c.Y--
|
||||
c.updateStatus(c.Y)
|
||||
}
|
||||
|
||||
// EOR: Exclusive-OR accumulator with memory.
|
||||
func (c *Cpu) EOR(in Instruction) {
|
||||
value := c.resolveOperand(in)
|
||||
c.A ^= value
|
||||
c.updateStatus(c.A)
|
||||
}
|
||||
|
||||
// INC: Increment.
|
||||
func (c *Cpu) INC(in Instruction) {
|
||||
address := c.memoryAddress(in)
|
||||
value := c.Bus.Read(address) + 1
|
||||
c.Bus.Write(address, value)
|
||||
c.updateStatus(value)
|
||||
}
|
||||
|
||||
// INX: Increment index register X.
|
||||
func (c *Cpu) INX(in Instruction) {
|
||||
c.X++
|
||||
c.updateStatus(c.X)
|
||||
}
|
||||
|
||||
// INY: Increment index register Y.
|
||||
func (c *Cpu) INY(in Instruction) {
|
||||
c.Y++
|
||||
c.updateStatus(c.Y)
|
||||
}
|
||||
|
||||
// JMP: Jump.
|
||||
func (c *Cpu) JMP(in Instruction) {
|
||||
c.PC = c.memoryAddress(in)
|
||||
}
|
||||
|
||||
// JSR: Jump to subroutine.
|
||||
func (c *Cpu) JSR(in Instruction) {
|
||||
c.Bus.Write16(c.stackHead(-1), c.PC-1)
|
||||
c.SP -= 2
|
||||
c.PC = in.Op16
|
||||
}
|
||||
|
||||
// LDA: Load accumulator from memory.
|
||||
func (c *Cpu) LDA(in Instruction) {
|
||||
c.A = c.resolveOperand(in)
|
||||
c.updateStatus(c.A)
|
||||
}
|
||||
|
||||
// LDX: Load index register X from memory.
|
||||
func (c *Cpu) LDX(in Instruction) {
|
||||
c.X = c.resolveOperand(in)
|
||||
c.updateStatus(c.X)
|
||||
}
|
||||
|
||||
// LDY: Load index register Y from memory.
|
||||
func (c *Cpu) LDY(in Instruction) {
|
||||
c.Y = c.resolveOperand(in)
|
||||
c.updateStatus(c.Y)
|
||||
}
|
||||
|
||||
// LSR: Logical shift memory or accumulator right.
|
||||
func (c *Cpu) LSR(in Instruction) {
|
||||
switch in.addressing {
|
||||
case accumulator:
|
||||
c.setStatus(sCarry, c.A&1 == 1)
|
||||
c.A >>= 1
|
||||
c.updateStatus(c.A)
|
||||
default:
|
||||
address := c.memoryAddress(in)
|
||||
value := c.Bus.Read(address)
|
||||
c.setStatus(sCarry, value&1 == 1)
|
||||
value >>= 1
|
||||
c.Bus.Write(address, value)
|
||||
c.updateStatus(value)
|
||||
}
|
||||
}
|
||||
|
||||
// NOP: No operation.
|
||||
func (c *Cpu) NOP(in Instruction) {
|
||||
}
|
||||
|
||||
// ORA: OR accumulator with memory.
|
||||
func (c *Cpu) ORA(in Instruction) {
|
||||
c.A |= c.resolveOperand(in)
|
||||
c.updateStatus(c.A)
|
||||
}
|
||||
|
||||
// PHA: Push accumulator onto stack.
|
||||
func (c *Cpu) PHA(in Instruction) {
|
||||
c.Bus.Write(0x0100+uint16(c.SP), c.A)
|
||||
c.SP--
|
||||
}
|
||||
|
||||
// PLA: Pull accumulator from stack.
|
||||
func (c *Cpu) PLA(in Instruction) {
|
||||
c.SP++
|
||||
c.A = c.Bus.Read(0x0100 + uint16(c.SP))
|
||||
}
|
||||
|
||||
// ROL: Rotate memory or accumulator left one bit.
|
||||
func (c *Cpu) ROL(in Instruction) {
|
||||
carry := c.getStatusInt(sCarry)
|
||||
switch in.addressing {
|
||||
case accumulator:
|
||||
c.setStatus(sCarry, c.A>>7 == 1)
|
||||
c.A = c.A<<1 | carry
|
||||
c.updateStatus(c.A)
|
||||
default:
|
||||
address := c.memoryAddress(in)
|
||||
value := c.Bus.Read(address)
|
||||
c.setStatus(sCarry, value>>7 == 1)
|
||||
value = value<<1 | carry
|
||||
c.Bus.Write(address, value)
|
||||
c.updateStatus(value)
|
||||
}
|
||||
}
|
||||
|
||||
// ROR: Rotate memory or accumulator left one bit.
|
||||
func (c *Cpu) ROR(in Instruction) {
|
||||
carry := c.getStatusInt(sCarry)
|
||||
switch in.addressing {
|
||||
case accumulator:
|
||||
c.setStatus(sCarry, c.A&1 == 1)
|
||||
c.A = c.A>>1 | carry<<7
|
||||
c.updateStatus(c.A)
|
||||
default:
|
||||
address := c.memoryAddress(in)
|
||||
value := c.Bus.Read(address)
|
||||
c.setStatus(sCarry, value&1 == 1)
|
||||
value = value>>1 | carry<<7
|
||||
c.Bus.Write(address, value)
|
||||
c.updateStatus(value)
|
||||
}
|
||||
}
|
||||
|
||||
// RTS: Return from subroutine.
|
||||
func (c *Cpu) RTS(in Instruction) {
|
||||
c.PC = c.Bus.Read16(c.stackHead(1))
|
||||
c.SP += 2
|
||||
c.PC += 1
|
||||
}
|
||||
|
||||
// SBC: Subtract memory with borrow from accumulator.
|
||||
func (c *Cpu) SBC(in Instruction) {
|
||||
valueSigned := int16(c.A) - int16(c.resolveOperand(in))
|
||||
if !c.getStatus(sCarry) {
|
||||
valueSigned--
|
||||
}
|
||||
c.A = uint8(valueSigned)
|
||||
|
||||
// v: Set if signed overflow; cleared if valid sign result.
|
||||
// TODO: c.setStatus(sOverflow, something)
|
||||
|
||||
// c: Set if unsigned borrow not required; cleared if unsigned borrow.
|
||||
c.setStatus(sCarry, valueSigned >= 0)
|
||||
|
||||
// n: Set if most significant bit of result is set; else cleared.
|
||||
// z: Set if result is zero; else cleared.
|
||||
c.updateStatus(c.A)
|
||||
}
|
||||
|
||||
// SEC: Set carry flag.
|
||||
func (c *Cpu) SEC(in Instruction) {
|
||||
c.setStatus(sCarry, true)
|
||||
}
|
||||
|
||||
// SEI: Set interrupt-disable flag.
|
||||
func (c *Cpu) SEI(in Instruction) {
|
||||
c.setStatus(sInterrupt, false)
|
||||
}
|
||||
|
||||
// STA: Store accumulator to memory.
|
||||
func (c *Cpu) STA(in Instruction) {
|
||||
c.Bus.Write(c.memoryAddress(in), c.A)
|
||||
}
|
||||
|
||||
// STX: Store index register X to memory.
|
||||
func (c *Cpu) STX(in Instruction) {
|
||||
c.Bus.Write(c.memoryAddress(in), c.X)
|
||||
}
|
||||
|
||||
// STY: Store index register Y to memory.
|
||||
func (c *Cpu) STY(in Instruction) {
|
||||
c.Bus.Write(c.memoryAddress(in), c.Y)
|
||||
}
|
||||
|
||||
// TAX: Transfer accumulator to index register X.
|
||||
func (c *Cpu) TAX(in Instruction) {
|
||||
c.X = c.A
|
||||
c.updateStatus(c.X)
|
||||
}
|
||||
|
||||
// TAY: Transfer accumulator to index register Y.
|
||||
func (c *Cpu) TAY(in Instruction) {
|
||||
c.Y = c.A
|
||||
c.updateStatus(c.Y)
|
||||
}
|
||||
|
||||
// TSX: Transfer stack pointer to index register X.
|
||||
func (c *Cpu) TSX(in Instruction) {
|
||||
c.X = c.SP
|
||||
c.updateStatus(c.X)
|
||||
}
|
||||
|
||||
// TXA: Transfer index register X to accumulator.
|
||||
func (c *Cpu) TXA(in Instruction) {
|
||||
c.A = c.X
|
||||
c.updateStatus(c.A)
|
||||
}
|
||||
|
||||
// TXS: Transfer index register X to stack pointer.
|
||||
func (c *Cpu) TXS(in Instruction) {
|
||||
c.SP = c.X
|
||||
c.updateStatus(c.SP)
|
||||
}
|
||||
|
||||
// TYA: Transfer index register Y to accumulator.
|
||||
func (c *Cpu) TYA(in Instruction) {
|
||||
c.A = c.Y
|
||||
c.updateStatus(c.A)
|
||||
}
|
||||
|
||||
func (c *Cpu) _END(in Instruction) {
|
||||
c.ExitChan <- int(c.X)
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
package cpu
|
||||
|
||||
import (
|
||||
"fmt"
|
||||
"github.com/ariejan/i6502/bus"
|
||||
)
|
||||
|
||||
// Instruction is a self-contained, variable length instruction,
|
||||
// it includes the the operation type and a possible 8 or 16 bit operand.
|
||||
type Instruction struct {
|
||||
OpType
|
||||
|
||||
// 2 byte instructions have a single byte operand
|
||||
Op8 uint8
|
||||
|
||||
// 3 byte instruction have a double byte operand
|
||||
Op16 uint16
|
||||
}
|
||||
|
||||
func ReadInstruction(pc uint16, bus *bus.Bus) Instruction {
|
||||
// Read the opcode
|
||||
opcode := bus.Read(pc)
|
||||
|
||||
// Do we know this opcode in our optypes table?
|
||||
optype, ok := optypes[opcode]
|
||||
if !ok {
|
||||
panic(fmt.Sprintf("Unknown opcode $%02X at $04X", opcode, pc))
|
||||
}
|
||||
|
||||
instruction := Instruction{OpType: optype}
|
||||
switch instruction.Bytes {
|
||||
case 1: // No operand.
|
||||
case 2:
|
||||
instruction.Op8 = bus.Read(pc + 1)
|
||||
case 3:
|
||||
instruction.Op16 = bus.Read16(pc + 1)
|
||||
default:
|
||||
panic(fmt.Sprintf("Unknown instruction length (%d) for $%02X at $04X", instruction.Bytes, opcode, pc))
|
||||
}
|
||||
|
||||
return instruction
|
||||
}
|
||||
|
|
@ -0,0 +1,340 @@
|
|||
package cpu
|
||||
|
||||
// 6502 Addressing modes
|
||||
const (
|
||||
_ = iota
|
||||
absolute
|
||||
absoluteX
|
||||
absoluteY
|
||||
accumulator
|
||||
immediate
|
||||
implied
|
||||
indirect
|
||||
indirectX
|
||||
indirectY
|
||||
relative
|
||||
zeropage
|
||||
zeropageX
|
||||
zeropageY
|
||||
)
|
||||
|
||||
// Human readable address modes
|
||||
var addressingNames = [...]string{
|
||||
"",
|
||||
"absolute",
|
||||
"absoluteX",
|
||||
"absoluteY",
|
||||
"accumulator",
|
||||
"immediate",
|
||||
"implied",
|
||||
"(indirect)",
|
||||
"(indirect,X)",
|
||||
"(indirect),Y",
|
||||
"relative",
|
||||
"zeropage",
|
||||
"zeropageX",
|
||||
"zeropageY",
|
||||
}
|
||||
|
||||
// 6502 Instruction mnemonics.
|
||||
// OpCodes are a combination of an instruction and an addressing mode
|
||||
const (
|
||||
_ = iota
|
||||
adc
|
||||
and
|
||||
asl
|
||||
bcc
|
||||
bcs
|
||||
beq
|
||||
bit
|
||||
bmi
|
||||
bne
|
||||
bpl
|
||||
brk
|
||||
bvc
|
||||
bvs
|
||||
clc
|
||||
cld
|
||||
cli
|
||||
clv
|
||||
cmp
|
||||
cpx
|
||||
cpy
|
||||
dec
|
||||
dex
|
||||
dey
|
||||
eor
|
||||
inc
|
||||
inx
|
||||
iny
|
||||
jmp
|
||||
jsr
|
||||
lda
|
||||
ldx
|
||||
ldy
|
||||
lsr
|
||||
nop
|
||||
ora
|
||||
pha
|
||||
php
|
||||
pla
|
||||
plp
|
||||
rol
|
||||
ror
|
||||
rti
|
||||
rts
|
||||
sbc
|
||||
sec
|
||||
sed
|
||||
sei
|
||||
sta
|
||||
stx
|
||||
sty
|
||||
tax
|
||||
tay
|
||||
tsx
|
||||
txa
|
||||
txs
|
||||
tya
|
||||
_end
|
||||
)
|
||||
|
||||
// Human readable instruction mnemonics
|
||||
var instructionNames = [...]string{
|
||||
"",
|
||||
"ADC",
|
||||
"AND",
|
||||
"ASL",
|
||||
"BCC",
|
||||
"BCS",
|
||||
"BEQ",
|
||||
"BIT",
|
||||
"BMI",
|
||||
"BNE",
|
||||
"BPL",
|
||||
"BRK",
|
||||
"BVC",
|
||||
"BVS",
|
||||
"CLC",
|
||||
"CLD",
|
||||
"CLI",
|
||||
"CLV",
|
||||
"CMP",
|
||||
"CPX",
|
||||
"CPY",
|
||||
"DEC",
|
||||
"DEX",
|
||||
"DEY",
|
||||
"EOR",
|
||||
"INC",
|
||||
"INX",
|
||||
"INY",
|
||||
"JMP",
|
||||
"JSR",
|
||||
"LDA",
|
||||
"LDX",
|
||||
"LDY",
|
||||
"LSR",
|
||||
"NOP",
|
||||
"ORA",
|
||||
"PHA",
|
||||
"PHP",
|
||||
"PLA",
|
||||
"PLP",
|
||||
"ROL",
|
||||
"ROR",
|
||||
"RTI",
|
||||
"RTS",
|
||||
"SBC",
|
||||
"SEC",
|
||||
"SED",
|
||||
"SEI",
|
||||
"STA",
|
||||
"STX",
|
||||
"STY",
|
||||
"TAX",
|
||||
"TAY",
|
||||
"TSX",
|
||||
"TXA",
|
||||
"TXS",
|
||||
"TYA",
|
||||
"_END",
|
||||
}
|
||||
|
||||
// The OpType consists of a 6502 instruction and addressing mode.
|
||||
// It does not include any following operand
|
||||
type OpType struct {
|
||||
// Opcode is the instruction + addresing mode
|
||||
Opcode byte
|
||||
|
||||
// Internal id for the used instruction/mnemonic
|
||||
id uint8
|
||||
|
||||
// Internal id for the addressing mode
|
||||
addressing uint8
|
||||
|
||||
// Bytes is the size of the instruction and its expected operands.
|
||||
// 1 byte: opcode with implicit or null operand
|
||||
// 2 bytes: opcode with immediate or zeropage operand (8-bit operand)
|
||||
// 3 bytes: opcode with address operands
|
||||
Bytes uint8
|
||||
|
||||
// Cycles, number of clock cycles it takes to execute this opcode
|
||||
Cycles uint8
|
||||
}
|
||||
|
||||
// See http://www.e-tradition.net/bytes/6502/6502_instruction_set.html for details
|
||||
var optypes = map[uint8]OpType{
|
||||
0x69: OpType{0x69, adc, immediate, 2, 2},
|
||||
0x65: OpType{0x69, adc, zeropage, 2, 3},
|
||||
0x75: OpType{0x75, adc, zeropageX, 2, 4},
|
||||
0x6D: OpType{0x6D, adc, absolute, 3, 4},
|
||||
0x7D: OpType{0x7D, adc, absoluteX, 3, 4},
|
||||
0x79: OpType{0x79, adc, absoluteY, 3, 4},
|
||||
0x61: OpType{0x61, adc, indirectX, 2, 6},
|
||||
0x71: OpType{0x71, adc, indirectY, 2, 5},
|
||||
0x29: OpType{0x29, and, immediate, 2, 2},
|
||||
0x25: OpType{0x25, and, zeropage, 2, 3},
|
||||
0x35: OpType{0x35, and, zeropageX, 2, 4},
|
||||
0x2D: OpType{0x2D, and, absolute, 3, 4},
|
||||
0x3D: OpType{0x3D, and, absoluteX, 3, 4},
|
||||
0x39: OpType{0x39, and, absoluteY, 3, 4},
|
||||
0x21: OpType{0x21, and, indirectX, 2, 6},
|
||||
0x31: OpType{0x31, and, indirectY, 2, 5},
|
||||
0x0A: OpType{0x0A, asl, accumulator, 1, 2},
|
||||
0x06: OpType{0x06, asl, zeropage, 2, 5},
|
||||
0x16: OpType{0x16, asl, zeropageX, 2, 6},
|
||||
0x0E: OpType{0x0E, asl, absolute, 3, 6},
|
||||
0x1E: OpType{0x1E, asl, absoluteX, 3, 7},
|
||||
0x90: OpType{0x90, bcc, relative, 2, 2},
|
||||
0xB0: OpType{0xB0, bcs, relative, 2, 2},
|
||||
0xF0: OpType{0xF0, beq, relative, 2, 2},
|
||||
0x24: OpType{0x24, bit, zeropage, 2, 3},
|
||||
0x2C: OpType{0x2C, bit, absolute, 3, 4},
|
||||
0x30: OpType{0x30, bmi, relative, 2, 2},
|
||||
0xD0: OpType{0xD0, bne, relative, 2, 2},
|
||||
0x10: OpType{0x10, bpl, relative, 2, 2},
|
||||
0x00: OpType{0x00, brk, implied, 1, 7},
|
||||
0x50: OpType{0x50, bvc, relative, 2, 2},
|
||||
0x70: OpType{0x70, bvs, relative, 2, 2},
|
||||
0x18: OpType{0x18, clc, implied, 1, 2},
|
||||
0xD8: OpType{0xD8, cld, implied, 1, 2},
|
||||
0x58: OpType{0x58, cli, implied, 1, 2},
|
||||
0xB8: OpType{0xB8, clv, implied, 1, 2},
|
||||
0xC9: OpType{0xC9, cmp, immediate, 2, 2},
|
||||
0xC5: OpType{0xC5, cmp, zeropage, 2, 3},
|
||||
0xD5: OpType{0xD5, cmp, zeropageX, 2, 4},
|
||||
0xCD: OpType{0xCD, cmp, absolute, 3, 4},
|
||||
0xDD: OpType{0xDD, cmp, absoluteX, 3, 4},
|
||||
0xD9: OpType{0xD9, cmp, absoluteY, 3, 4},
|
||||
0xC1: OpType{0xC1, cmp, indirectX, 2, 6},
|
||||
0xD1: OpType{0xD1, cmp, indirectY, 2, 5},
|
||||
0xE0: OpType{0xE0, cpx, immediate, 2, 2},
|
||||
0xE4: OpType{0xE4, cpx, zeropage, 2, 3},
|
||||
0xEC: OpType{0xEC, cpx, absolute, 3, 4},
|
||||
0xC0: OpType{0xC0, cpy, immediate, 2, 2},
|
||||
0xC4: OpType{0xC4, cpy, zeropage, 2, 3},
|
||||
0xCC: OpType{0xCC, cpy, absolute, 3, 4},
|
||||
0xC6: OpType{0xC6, dec, zeropage, 2, 5},
|
||||
0xD6: OpType{0xD6, dec, zeropageX, 2, 6},
|
||||
0xCE: OpType{0xCE, dec, absolute, 3, 3},
|
||||
0xDE: OpType{0xDE, dec, absoluteX, 3, 7},
|
||||
0xCA: OpType{0xCA, dex, implied, 1, 2},
|
||||
0x88: OpType{0x88, dey, implied, 1, 2},
|
||||
0x49: OpType{0x49, eor, immediate, 2, 2},
|
||||
0x45: OpType{0x45, eor, zeropage, 2, 3},
|
||||
0x55: OpType{0x55, eor, zeropageX, 2, 4},
|
||||
0x4D: OpType{0x4D, eor, absolute, 3, 4},
|
||||
0x5D: OpType{0x5D, eor, absoluteX, 3, 4},
|
||||
0x59: OpType{0x59, eor, absoluteY, 3, 4},
|
||||
0x41: OpType{0x41, eor, indirectX, 2, 6},
|
||||
0x51: OpType{0x51, eor, indirectY, 2, 5},
|
||||
0xE6: OpType{0xE6, inc, zeropage, 2, 5},
|
||||
0xF6: OpType{0xF6, inc, zeropageX, 2, 6},
|
||||
0xEE: OpType{0xEE, inc, absolute, 3, 6},
|
||||
0xFE: OpType{0xFE, inc, absoluteX, 3, 7},
|
||||
0xE8: OpType{0xE8, inx, implied, 1, 2},
|
||||
0xC8: OpType{0xC8, iny, implied, 1, 2},
|
||||
0x4C: OpType{0x4C, jmp, absolute, 3, 3},
|
||||
0x6C: OpType{0x6C, jmp, indirect, 3, 5},
|
||||
0x20: OpType{0x20, jsr, absolute, 3, 6},
|
||||
0xA9: OpType{0xA9, lda, immediate, 2, 2},
|
||||
0xA5: OpType{0xA5, lda, zeropage, 2, 3},
|
||||
0xB5: OpType{0xB5, lda, zeropageX, 2, 4},
|
||||
0xAD: OpType{0xAD, lda, absolute, 3, 4},
|
||||
0xBD: OpType{0xBD, lda, absoluteX, 3, 4},
|
||||
0xB9: OpType{0xB9, lda, absoluteY, 3, 4},
|
||||
0xA1: OpType{0xA1, lda, indirectX, 2, 6},
|
||||
0xB1: OpType{0xB1, lda, indirectY, 2, 5},
|
||||
0xA2: OpType{0xA2, ldx, immediate, 2, 2},
|
||||
0xA6: OpType{0xA6, ldx, zeropage, 2, 3},
|
||||
0xB6: OpType{0xB6, ldx, zeropageY, 2, 4},
|
||||
0xAE: OpType{0xAE, ldx, absolute, 3, 4},
|
||||
0xBE: OpType{0xBE, ldx, absoluteY, 3, 4},
|
||||
0xA0: OpType{0xA0, ldy, immediate, 2, 2},
|
||||
0xA4: OpType{0xA4, ldy, zeropage, 2, 3},
|
||||
0xB4: OpType{0xB4, ldy, zeropageX, 2, 4},
|
||||
0xAC: OpType{0xAC, ldy, absolute, 3, 4},
|
||||
0xBC: OpType{0xBC, ldy, absoluteX, 3, 4},
|
||||
0x4A: OpType{0x4A, lsr, accumulator, 1, 2},
|
||||
0x46: OpType{0x46, lsr, zeropage, 2, 5},
|
||||
0x56: OpType{0x56, lsr, zeropageX, 2, 6},
|
||||
0x4E: OpType{0x4E, lsr, absolute, 3, 6},
|
||||
0x5E: OpType{0x5E, lsr, absoluteX, 3, 7},
|
||||
0xEA: OpType{0xEA, nop, implied, 1, 2},
|
||||
0x09: OpType{0x09, ora, immediate, 2, 2},
|
||||
0x05: OpType{0x05, ora, zeropage, 2, 3},
|
||||
0x15: OpType{0x15, ora, zeropageX, 2, 4},
|
||||
0x0D: OpType{0x0D, ora, absolute, 3, 4},
|
||||
0x1D: OpType{0x1D, ora, absoluteX, 3, 4},
|
||||
0x19: OpType{0x19, ora, absoluteY, 3, 4},
|
||||
0x01: OpType{0x01, ora, indirectX, 2, 6},
|
||||
0x11: OpType{0x11, ora, indirectY, 2, 5},
|
||||
0x48: OpType{0x48, pha, implied, 1, 3},
|
||||
0x08: OpType{0x08, php, implied, 1, 3},
|
||||
0x68: OpType{0x68, pla, implied, 1, 4},
|
||||
0x28: OpType{0x28, php, implied, 1, 4},
|
||||
0x2A: OpType{0x2A, rol, accumulator, 1, 2},
|
||||
0x26: OpType{0x26, rol, zeropage, 2, 5},
|
||||
0x36: OpType{0x36, rol, zeropageX, 2, 6},
|
||||
0x2E: OpType{0x2E, rol, absolute, 3, 6},
|
||||
0x3E: OpType{0x3E, rol, absoluteX, 3, 7},
|
||||
0x6A: OpType{0x6A, ror, accumulator, 1, 2},
|
||||
0x66: OpType{0x66, ror, zeropage, 2, 5},
|
||||
0x76: OpType{0x76, ror, zeropageX, 2, 6},
|
||||
0x6E: OpType{0x6E, ror, absolute, 3, 6},
|
||||
0x7E: OpType{0x7E, ror, absoluteX, 3, 7},
|
||||
0x40: OpType{0x40, rti, implied, 1, 6},
|
||||
0x60: OpType{0x60, rts, implied, 1, 6},
|
||||
0xE9: OpType{0xE9, sbc, immediate, 2, 2},
|
||||
0xE5: OpType{0xE5, sbc, zeropage, 2, 3},
|
||||
0xF5: OpType{0xF5, sbc, zeropageX, 2, 4},
|
||||
0xED: OpType{0xED, sbc, absolute, 3, 4},
|
||||
0xFD: OpType{0xFD, sbc, absoluteX, 3, 4},
|
||||
0xF9: OpType{0xF9, sbc, absoluteY, 3, 4},
|
||||
0xE1: OpType{0xE1, sbc, indirectX, 2, 6},
|
||||
0xF1: OpType{0xF1, sbc, indirectY, 2, 5},
|
||||
0x38: OpType{0x38, sec, implied, 1, 2},
|
||||
0xF8: OpType{0xF8, sed, implied, 1, 2},
|
||||
0x78: OpType{0x78, sei, implied, 1, 2},
|
||||
0x85: OpType{0x85, sta, zeropage, 2, 3},
|
||||
0x95: OpType{0x95, sta, zeropageX, 2, 4},
|
||||
0x8D: OpType{0x8D, sta, absolute, 3, 4},
|
||||
0x9D: OpType{0x9D, sta, absoluteX, 3, 5},
|
||||
0x99: OpType{0x99, sta, absoluteY, 3, 5},
|
||||
0x81: OpType{0x81, sta, indirectX, 2, 6},
|
||||
0x91: OpType{0x91, sta, indirectY, 2, 6},
|
||||
0x86: OpType{0x86, stx, zeropage, 2, 3},
|
||||
0x96: OpType{0x96, stx, zeropageY, 2, 4},
|
||||
0x8E: OpType{0x8E, stx, absolute, 3, 4},
|
||||
0x84: OpType{0x84, sty, zeropage, 2, 3},
|
||||
0x94: OpType{0x94, sty, zeropageX, 2, 4},
|
||||
0x8C: OpType{0x8C, sty, absolute, 3, 4},
|
||||
0xAA: OpType{0xAA, tax, implied, 1, 2},
|
||||
0xA8: OpType{0xA8, tay, implied, 1, 2},
|
||||
0xBA: OpType{0xBA, tsx, implied, 1, 2},
|
||||
0x8A: OpType{0x8A, txa, implied, 1, 2},
|
||||
0x9A: OpType{0x9A, txs, implied, 1, 2},
|
||||
0x98: OpType{0x98, tya, implied, 1, 2},
|
||||
0xFF: OpType{0xFF, _end, implied, 1, 1},
|
||||
}
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
i6502 is a software emulator of my i6502 home-built computer. It uses
|
||||
the 65C02 microprocessor, 32kB RAM and 16kB ROM.
|
||||
*/
|
||||
package main
|
||||
|
||||
import (
|
||||
"fmt"
|
||||
"github.com/ariejan/i6502/bus"
|
||||
"github.com/ariejan/i6502/cpu"
|
||||
"github.com/ariejan/i6502/memory"
|
||||
"os"
|
||||
"os/signal"
|
||||
)
|
||||
|
||||
func main() {
|
||||
os.Exit(mainReturningStatus())
|
||||
}
|
||||
|
||||
func mainReturningStatus() int {
|
||||
// 32kB RAM
|
||||
ram := memory.CreateRam()
|
||||
|
||||
// 16kB ROM, filled from file
|
||||
rom, err := memory.LoadRomFromFile("rom/test.rom")
|
||||
if err != nil {
|
||||
panic(err)
|
||||
}
|
||||
|
||||
// 16-bit address bus
|
||||
bus, _ := bus.CreateBus()
|
||||
bus.Attach(ram, "32kB RAM", 0x0000)
|
||||
bus.Attach(rom, "16kB ROM", 0xC000)
|
||||
|
||||
fmt.Println(bus)
|
||||
|
||||
exitChan := make(chan int, 0)
|
||||
|
||||
cpu := &cpu.Cpu{Bus: bus, ExitChan: exitChan}
|
||||
cpu.Reset()
|
||||
|
||||
go func() {
|
||||
for {
|
||||
cpu.Step()
|
||||
}
|
||||
}()
|
||||
|
||||
var (
|
||||
sig os.Signal
|
||||
exitStatus int
|
||||
)
|
||||
|
||||
sigChan := make(chan os.Signal, 1)
|
||||
signal.Notify(sigChan, os.Interrupt)
|
||||
|
||||
select {
|
||||
case exitStatus = <-exitChan:
|
||||
// Okay, handle the rest of the code
|
||||
case sig = <-sigChan:
|
||||
fmt.Println("\nGot signal: ", sig)
|
||||
exitStatus = 1
|
||||
}
|
||||
|
||||
fmt.Println(cpu)
|
||||
fmt.Println("Dumping RAM into `core` file")
|
||||
ram.Dump("core")
|
||||
|
||||
return exitStatus
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
// Package memory provides different memory components
|
||||
// and a common interface.
|
||||
package memory
|
||||
|
||||
type Memory interface {
|
||||
Size() int
|
||||
Read(address uint16) byte
|
||||
Write(address uint16, value byte)
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
package memory
|
||||
|
||||
import (
|
||||
"io/ioutil"
|
||||
)
|
||||
|
||||
// Ram provides 32kB of Random Access Memory
|
||||
type Ram struct {
|
||||
data [0x8000]byte
|
||||
}
|
||||
|
||||
func (ram *Ram) Size() int {
|
||||
return len(ram.data)
|
||||
}
|
||||
|
||||
func (ram *Ram) Read(address uint16) byte {
|
||||
return ram.data[address]
|
||||
}
|
||||
|
||||
func (ram *Ram) Write(address uint16, value byte) {
|
||||
ram.data[address] = value
|
||||
}
|
||||
|
||||
func CreateRam() *Ram {
|
||||
return &Ram{}
|
||||
}
|
||||
|
||||
func (ram *Ram) Dump(path string) {
|
||||
err := ioutil.WriteFile(path, ram.data[:], 0640)
|
||||
if err != nil {
|
||||
panic(err)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
package memory
|
||||
|
||||
import (
|
||||
"io/ioutil"
|
||||
)
|
||||
|
||||
// Rom provies 16kB of Read Only Memory, typcially loaded from file.
|
||||
type Rom struct {
|
||||
data [0x4000]byte
|
||||
}
|
||||
|
||||
func (rom *Rom) Size() int {
|
||||
return len(rom.data)
|
||||
}
|
||||
|
||||
func (rom *Rom) Read(address uint16) byte {
|
||||
return rom.data[address]
|
||||
}
|
||||
|
||||
func (rom *Rom) Write(address uint16, value byte) {
|
||||
panic("Cannot write to ROM!")
|
||||
}
|
||||
|
||||
// Load ROM from a binary file. The data is placed
|
||||
// at the beginning of ROM.
|
||||
func LoadRomFromFile(path string) (*Rom, error) {
|
||||
// Read data from file
|
||||
data, err := ioutil.ReadFile(path)
|
||||
if err != nil {
|
||||
return nil, err
|
||||
}
|
||||
|
||||
// Create the rom instance
|
||||
rom := &Rom{}
|
||||
|
||||
// Load data into ROM
|
||||
for i, b := range data {
|
||||
rom.data[i] = b
|
||||
}
|
||||
|
||||
return rom, nil
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
../../asm/build/kernal.rom
|
||||
Loading…
Reference in New Issue