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llvm-6502/test/CodeGen/ARM/fp16.ll

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Feature test for half precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:43 +00:00
; RUN: llc < %s | FileCheck %s
Fix typo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:52 +00:00
; RUN: llc -mattr=+vfp3,+fp16 < %s | FileCheck --check-prefix=CHECK-FP16 %s
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
; RUN: llc -mtriple=armv8-eabi < %s | FileCheck --check-prefix=CHECK-ARMV8 %s
ARM: fix @llvm.convert.from.fp16 on softfloat targets. We need to make sure we use the softened version of all appropriate operands in the libcall, or things go horribly wrong. This may entail actually executing a 1-stage softening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:38 +00:00
; RUN: llc -mtriple=thumbv7m-eabi < %s | FileCheck --check-prefix=CHECK-SOFTFLOAT %s
Feature test for half precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:43 +00:00
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "armv7-eabi"
@x = global i16 12902
@y = global i16 0
@z = common global i16 0
define arm_aapcs_vfpcc void @foo() nounwind {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 06:24:09 +00:00
; CHECK-LABEL: foo:
Fix more broken CHECK lines git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201493 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 13:28:39 +00:00
; CHECK-FP16-LABEL: foo:
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
; CHECK-ARMV8-LABEL: foo:
ARM: fix @llvm.convert.from.fp16 on softfloat targets. We need to make sure we use the softened version of all appropriate operands in the libcall, or things go horribly wrong. This may entail actually executing a 1-stage softening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:38 +00:00
; CHECK-SOFTFLOAT-LABEL: foo:
Feature test for half precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:43 +00:00
entry:
%0 = load i16* @x, align 2
%1 = load i16* @y, align 2
CodeGen: extend f16 conversions to permit types > float. This makes the two intrinsics @llvm.convert.from.f16 and @llvm.convert.to.f16 accept types other than simple "float". This is only strictly needed for the truncate operation, since otherwise double rounding occurs and there's no way to represent the strict IEEE conversion. However, for symmetry we allow larger types in the extend too. During legalization, we can expand an "fp16_to_double" operation into two extends for convenience, but abort when the truncate isn't legal. A new libcall is probably needed here. Even after this commit, various target tweaks are needed to actually use the extended intrinsics. I've put these into separate commits for clarity, so there are no actual tests of f64 conversion here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:51:23 +00:00
%2 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
Feature test for half precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:43 +00:00
; CHECK: __gnu_h2f_ieee
The names of VFP variants of half-to-float conversion instructions were reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14 23:36:01 +00:00
; CHECK-FP16: vcvtb.f32.f16
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
; CHECK-ARMv8: vcvtb.f32.f16
ARM: fix @llvm.convert.from.fp16 on softfloat targets. We need to make sure we use the softened version of all appropriate operands in the libcall, or things go horribly wrong. This may entail actually executing a 1-stage softening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:38 +00:00
; CHECK-SOFTFLOAT: __gnu_h2f_ieee
CodeGen: extend f16 conversions to permit types > float. This makes the two intrinsics @llvm.convert.from.f16 and @llvm.convert.to.f16 accept types other than simple "float". This is only strictly needed for the truncate operation, since otherwise double rounding occurs and there's no way to represent the strict IEEE conversion. However, for symmetry we allow larger types in the extend too. During legalization, we can expand an "fp16_to_double" operation into two extends for convenience, but abort when the truncate isn't legal. A new libcall is probably needed here. Even after this commit, various target tweaks are needed to actually use the extended intrinsics. I've put these into separate commits for clarity, so there are no actual tests of f64 conversion here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:51:23 +00:00
%3 = tail call float @llvm.convert.from.fp16.f32(i16 %1)
Feature test for half precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:43 +00:00
; CHECK: __gnu_h2f_ieee
The names of VFP variants of half-to-float conversion instructions were reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14 23:36:01 +00:00
; CHECK-FP16: vcvtb.f32.f16
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
; CHECK-ARMV8: vcvtb.f32.f16
ARM: fix @llvm.convert.from.fp16 on softfloat targets. We need to make sure we use the softened version of all appropriate operands in the libcall, or things go horribly wrong. This may entail actually executing a 1-stage softening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:38 +00:00
; CHECK-SOFTFLOAT: __gnu_h2f_ieee
Feature test for half precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:43 +00:00
%4 = fadd float %2, %3
CodeGen: extend f16 conversions to permit types > float. This makes the two intrinsics @llvm.convert.from.f16 and @llvm.convert.to.f16 accept types other than simple "float". This is only strictly needed for the truncate operation, since otherwise double rounding occurs and there's no way to represent the strict IEEE conversion. However, for symmetry we allow larger types in the extend too. During legalization, we can expand an "fp16_to_double" operation into two extends for convenience, but abort when the truncate isn't legal. A new libcall is probably needed here. Even after this commit, various target tweaks are needed to actually use the extended intrinsics. I've put these into separate commits for clarity, so there are no actual tests of f64 conversion here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:51:23 +00:00
%5 = tail call i16 @llvm.convert.to.fp16.f32(float %4)
Feature test for half precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:43 +00:00
; CHECK: __gnu_f2h_ieee
The names of VFP variants of half-to-float conversion instructions were reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14 23:36:01 +00:00
; CHECK-FP16: vcvtb.f16.f32
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
; CHECK-ARMV8: vcvtb.f16.f32
ARM: fix @llvm.convert.from.fp16 on softfloat targets. We need to make sure we use the softened version of all appropriate operands in the libcall, or things go horribly wrong. This may entail actually executing a 1-stage softening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:38 +00:00
; CHECK-SOFTFLOAT: __gnu_f2h_ieee
Feature test for half precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:43 +00:00
store i16 %5, i16* @x, align 2
ret void
}
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
define arm_aapcs_vfpcc double @test_from_fp16(i16 %in) {
; CHECK-LABEL: test_from_fp16:
; CHECK-FP-LABEL: test_from_fp16:
; CHECK-ARMV8-LABEL: test_from_fp16:
ARM: fix @llvm.convert.from.fp16 on softfloat targets. We need to make sure we use the softened version of all appropriate operands in the libcall, or things go horribly wrong. This may entail actually executing a 1-stage softening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:38 +00:00
; CHECK-SOFTFLOAT-LABEL: test_from_fp16:
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
%val = call double @llvm.convert.from.fp16.f64(i16 %in)
; CHECK: bl __gnu_h2f_ieee
; CHECK: vmov [[TMP:s[0-9]+]], r0
; CHECK: vcvt.f64.f32 d0, [[TMP]]
; CHECK-FP16: vmov [[TMP16:s[0-9]+]], r0
; CHECK-FP16: vcvtb.f32.f16 [[TMP32:s[0-9]+]], [[TMP16]]
; CHECK-FP16: vcvt.f64.f32 d0, [[TMP32]]
; CHECK-ARMV8: vmov [[TMP:s[0-9]+]], r0
; CHECK-ARMV8: vcvtb.f64.f16 d0, [[TMP]]
ARM: fix @llvm.convert.from.fp16 on softfloat targets. We need to make sure we use the softened version of all appropriate operands in the libcall, or things go horribly wrong. This may entail actually executing a 1-stage softening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:38 +00:00
; CHECK-SOFTFLOAT: bl __gnu_h2f_ieee
; CHECK-SOFTFLOAT: bl __aeabi_f2d
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
ret double %val
}
define arm_aapcs_vfpcc i16 @test_to_fp16(double %in) {
; CHECK-LABEL: test_to_fp16:
; CHECK-FP-LABEL: test_to_fp16:
; CHECK-ARMV8-LABEL: test_to_fp16:
ARM: fix @llvm.convert.from.fp16 on softfloat targets. We need to make sure we use the softened version of all appropriate operands in the libcall, or things go horribly wrong. This may entail actually executing a 1-stage softening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:38 +00:00
; CHECK-SOFTFLOAT-LABEL: test_to_fp16:
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
%val = call i16 @llvm.convert.to.fp16.f64(double %in)
; CHECK: bl __truncdfhf2
; CHECK-FP16: bl __truncdfhf2
; CHECK-ARMV8: vcvtb.f16.f64 [[TMP:s[0-9]+]], d0
; CHECK-ARMV8: vmov r0, [[TMP]]
ARM: fix @llvm.convert.from.fp16 on softfloat targets. We need to make sure we use the softened version of all appropriate operands in the libcall, or things go horribly wrong. This may entail actually executing a 1-stage softening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214175 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:38 +00:00
ARM: add __aeabi_d2h for truncation on AEABI systems ARM does actually define the name for this conversion, so we should use it on "-eabi" platforms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214176 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 09:56:45 +00:00
; CHECK-SOFTFLOAT: bl __aeabi_d2h
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
ret i16 %val
}
CodeGen: extend f16 conversions to permit types > float. This makes the two intrinsics @llvm.convert.from.f16 and @llvm.convert.to.f16 accept types other than simple "float". This is only strictly needed for the truncate operation, since otherwise double rounding occurs and there's no way to represent the strict IEEE conversion. However, for symmetry we allow larger types in the extend too. During legalization, we can expand an "fp16_to_double" operation into two extends for convenience, but abort when the truncate isn't legal. A new libcall is probably needed here. Even after this commit, various target tweaks are needed to actually use the extended intrinsics. I've put these into separate commits for clarity, so there are no actual tests of f64 conversion here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:51:23 +00:00
declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
Feature test for half precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 18:42:43 +00:00
CodeGen: extend f16 conversions to permit types > float. This makes the two intrinsics @llvm.convert.from.f16 and @llvm.convert.to.f16 accept types other than simple "float". This is only strictly needed for the truncate operation, since otherwise double rounding occurs and there's no way to represent the strict IEEE conversion. However, for symmetry we allow larger types in the extend too. During legalization, we can expand an "fp16_to_double" operation into two extends for convenience, but abort when the truncate isn't legal. A new libcall is probably needed here. Even after this commit, various target tweaks are needed to actually use the extended intrinsics. I've put these into separate commits for clarity, so there are no actual tests of f64 conversion here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:51:23 +00:00
declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
ARM: support direct f16 <-> f64 conversions ARMv8 has instructions to handle it, otherwise a libcall is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:27:04 +00:00
declare i16 @llvm.convert.to.fp16.f64(double) nounwind readnone
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