2012-12-11 21:25:42 +00:00
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//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Custom DAG lowering for SI
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//
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//===----------------------------------------------------------------------===//
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#include "SIISelLowering.h"
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#include "AMDIL.h"
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2013-03-07 09:04:14 +00:00
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#include "AMDGPU.h"
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2012-12-11 21:25:42 +00:00
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#include "AMDILIntrinsicInfo.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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2013-03-07 09:03:52 +00:00
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#include "llvm/IR/Function.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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2012-12-11 21:25:42 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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using namespace llvm;
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SITargetLowering::SITargetLowering(TargetMachine &TM) :
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AMDGPUTargetLowering(TM),
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2013-02-26 17:52:23 +00:00
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TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
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TRI(TM.getRegisterInfo()) {
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2013-03-07 09:03:38 +00:00
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2013-02-16 11:28:30 +00:00
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addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
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2013-03-07 09:03:38 +00:00
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addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
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addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass);
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addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
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addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
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addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
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addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
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2012-12-11 21:25:42 +00:00
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2013-02-07 17:02:09 +00:00
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addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
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2013-03-07 09:03:38 +00:00
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2013-02-07 17:02:09 +00:00
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addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass);
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2013-03-07 09:03:38 +00:00
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addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
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2013-02-07 17:02:09 +00:00
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addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
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2013-03-07 09:03:38 +00:00
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addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
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2013-02-07 17:02:09 +00:00
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addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
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2013-03-07 09:03:38 +00:00
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addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
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2013-02-07 17:02:09 +00:00
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addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
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2013-03-07 09:03:38 +00:00
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addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
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2012-12-11 21:25:42 +00:00
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computeRegisterProperties();
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2013-03-18 11:34:16 +00:00
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
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2012-12-11 21:25:42 +00:00
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setOperationAction(ISD::ADD, MVT::i64, Legal);
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setOperationAction(ISD::ADD, MVT::i32, Legal);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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2013-03-08 10:58:01 +00:00
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2013-03-26 14:04:02 +00:00
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setSchedulingPreference(Sched::RegPressure);
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2012-12-11 21:25:42 +00:00
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}
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2013-03-07 09:03:52 +00:00
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SDValue SITargetLowering::LowerFormalArguments(
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SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
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MachineFunction &MF = DAG.getMachineFunction();
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FunctionType *FType = MF.getFunction()->getFunctionType();
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2013-03-07 09:04:14 +00:00
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SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
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2013-03-07 09:03:52 +00:00
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assert(CallConv == CallingConv::C);
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SmallVector<ISD::InputArg, 16> Splits;
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2013-03-07 09:04:14 +00:00
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uint32_t Skipped = 0;
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for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
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2013-03-07 09:03:52 +00:00
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const ISD::InputArg &Arg = Ins[i];
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2013-03-07 09:04:14 +00:00
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// First check if it's a PS input addr
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if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg()) {
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assert((PSInputNum <= 15) && "Too many PS inputs!");
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if (!Arg.Used) {
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// We can savely skip PS inputs
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Skipped |= 1 << i;
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++PSInputNum;
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continue;
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}
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Info->PSInputAddr |= 1 << PSInputNum++;
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}
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// Second split vertices into their elements
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2013-03-07 09:03:52 +00:00
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if (Arg.VT.isVector()) {
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ISD::InputArg NewArg = Arg;
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NewArg.Flags.setSplit();
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NewArg.VT = Arg.VT.getVectorElementType();
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// We REALLY want the ORIGINAL number of vertex elements here, e.g. a
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// three or five element vertex only needs three or five registers,
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// NOT four or eigth.
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Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
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unsigned NumElements = ParamType->getVectorNumElements();
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for (unsigned j = 0; j != NumElements; ++j) {
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Splits.push_back(NewArg);
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NewArg.PartOffset += NewArg.VT.getStoreSize();
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}
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} else {
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Splits.push_back(Arg);
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}
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}
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), ArgLocs, *DAG.getContext());
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2013-03-07 09:04:14 +00:00
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// At least one interpolation mode must be enabled or else the GPU will hang.
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if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) {
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Info->PSInputAddr |= 1;
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CCInfo.AllocateReg(AMDGPU::VGPR0);
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CCInfo.AllocateReg(AMDGPU::VGPR1);
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}
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2013-03-07 09:03:52 +00:00
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AnalyzeFormalArguments(CCInfo, Splits);
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for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
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2013-03-07 09:04:14 +00:00
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if (Skipped & (1 << i)) {
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InVals.push_back(SDValue());
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continue;
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}
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2013-03-07 09:03:52 +00:00
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CCValAssign &VA = ArgLocs[ArgIdx++];
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assert(VA.isRegLoc() && "Parameter must be in a register!");
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unsigned Reg = VA.getLocReg();
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MVT VT = VA.getLocVT();
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if (VT == MVT::i64) {
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// For now assume it is a pointer
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Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
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&AMDGPU::SReg_64RegClass);
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Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
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InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
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continue;
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}
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
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Reg = MF.addLiveIn(Reg, RC);
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SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
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const ISD::InputArg &Arg = Ins[i];
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if (Arg.VT.isVector()) {
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// Build a vector from the registers
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Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
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unsigned NumElements = ParamType->getVectorNumElements();
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SmallVector<SDValue, 4> Regs;
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Regs.push_back(Val);
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for (unsigned j = 1; j != NumElements; ++j) {
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Reg = ArgLocs[ArgIdx++].getLocReg();
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Reg = MF.addLiveIn(Reg, RC);
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Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
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}
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// Fill up the missing vector elements
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NumElements = Arg.VT.getVectorNumElements() - NumElements;
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for (unsigned j = 0; j != NumElements; ++j)
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Regs.push_back(DAG.getUNDEF(VT));
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InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT,
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Regs.data(), Regs.size()));
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continue;
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}
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InVals.push_back(Val);
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}
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return Chain;
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}
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2012-12-11 21:25:42 +00:00
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MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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MachineInstr * MI, MachineBasicBlock * BB) const {
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switch (MI->getOpcode()) {
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default:
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return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
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case AMDGPU::BRANCH: return BB;
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}
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return BB;
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}
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EVT SITargetLowering::getSetCCResultType(EVT VT) const {
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return MVT::i1;
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}
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2013-03-18 11:34:05 +00:00
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MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
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return MVT::i32;
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}
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2012-12-11 21:25:42 +00:00
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//===----------------------------------------------------------------------===//
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// Custom DAG Lowering Operations
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//===----------------------------------------------------------------------===//
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SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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2012-12-19 22:10:31 +00:00
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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2012-12-11 21:25:42 +00:00
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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}
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return SDValue();
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}
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2012-12-19 22:10:31 +00:00
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/// \brief Helper function for LowerBRCOND
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static SDNode *findUser(SDValue Value, unsigned Opcode) {
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SDNode *Parent = Value.getNode();
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for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
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I != E; ++I) {
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if (I.getUse().get() != Value)
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continue;
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if (I->getOpcode() == Opcode)
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return *I;
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}
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return 0;
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}
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/// This transforms the control flow intrinsics to get the branch destination as
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/// last parameter, also switches branch target with BR if the need arise
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SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
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SelectionDAG &DAG) const {
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DebugLoc DL = BRCOND.getDebugLoc();
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SDNode *Intr = BRCOND.getOperand(1).getNode();
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SDValue Target = BRCOND.getOperand(2);
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SDNode *BR = 0;
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if (Intr->getOpcode() == ISD::SETCC) {
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// As long as we negate the condition everything is fine
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SDNode *SetCC = Intr;
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assert(SetCC->getConstantOperandVal(1) == 1);
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2013-01-07 11:14:44 +00:00
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assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
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ISD::SETNE);
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2012-12-19 22:10:31 +00:00
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Intr = SetCC->getOperand(0).getNode();
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} else {
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// Get the target from BR if we don't negate the condition
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BR = findUser(BRCOND, ISD::BR);
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Target = BR->getOperand(1);
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}
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assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
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// Build the result and
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SmallVector<EVT, 4> Res;
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for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
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Res.push_back(Intr->getValueType(i));
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// operands of the new intrinsic call
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SmallVector<SDValue, 4> Ops;
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Ops.push_back(BRCOND.getOperand(0));
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for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
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Ops.push_back(Intr->getOperand(i));
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Ops.push_back(Target);
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// build the new intrinsic call
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SDNode *Result = DAG.getNode(
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Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
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DAG.getVTList(Res.data(), Res.size()), Ops.data(), Ops.size()).getNode();
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if (BR) {
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// Give the branch instruction our target
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SDValue Ops[] = {
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BR->getOperand(0),
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BRCOND.getOperand(2)
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};
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DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops, 2);
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}
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SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
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// Copy the intrinsic results to registers
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for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
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SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
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if (!CopyToReg)
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continue;
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Chain = DAG.getCopyToReg(
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Chain, DL,
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CopyToReg->getOperand(1),
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SDValue(Result, i - 1),
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SDValue());
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DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
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|
}
|
|
|
|
|
|
|
|
// Remove the old intrinsic from the chain
|
|
|
|
DAG.ReplaceAllUsesOfValueWith(
|
|
|
|
SDValue(Intr, Intr->getNumValues() - 1),
|
|
|
|
Intr->getOperand(0));
|
|
|
|
|
|
|
|
return Chain;
|
2012-12-11 21:25:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
|
|
|
|
SDValue LHS = Op.getOperand(0);
|
|
|
|
SDValue RHS = Op.getOperand(1);
|
|
|
|
SDValue True = Op.getOperand(2);
|
|
|
|
SDValue False = Op.getOperand(3);
|
|
|
|
SDValue CC = Op.getOperand(4);
|
|
|
|
EVT VT = Op.getValueType();
|
|
|
|
DebugLoc DL = Op.getDebugLoc();
|
|
|
|
|
|
|
|
// Possible Min/Max pattern
|
|
|
|
SDValue MinMax = LowerMinMax(Op, DAG);
|
|
|
|
if (MinMax.getNode()) {
|
|
|
|
return MinMax;
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
|
|
|
|
return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Custom DAG optimizations
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
|
|
|
|
DAGCombinerInfo &DCI) const {
|
|
|
|
SelectionDAG &DAG = DCI.DAG;
|
|
|
|
DebugLoc DL = N->getDebugLoc();
|
|
|
|
EVT VT = N->getValueType(0);
|
|
|
|
|
|
|
|
switch (N->getOpcode()) {
|
|
|
|
default: break;
|
|
|
|
case ISD::SELECT_CC: {
|
|
|
|
N->dump();
|
|
|
|
ConstantSDNode *True, *False;
|
|
|
|
// i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
|
|
|
|
if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
|
|
|
|
&& (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
|
|
|
|
&& True->isAllOnesValue()
|
|
|
|
&& False->isNullValue()
|
|
|
|
&& VT == MVT::i1) {
|
|
|
|
return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
|
|
|
|
N->getOperand(1), N->getOperand(4));
|
|
|
|
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SETCC: {
|
|
|
|
SDValue Arg0 = N->getOperand(0);
|
|
|
|
SDValue Arg1 = N->getOperand(1);
|
|
|
|
SDValue CC = N->getOperand(2);
|
|
|
|
ConstantSDNode * C = NULL;
|
|
|
|
ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
|
|
|
|
|
|
|
|
// i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
|
|
|
if (VT == MVT::i1
|
|
|
|
&& Arg0.getOpcode() == ISD::SIGN_EXTEND
|
|
|
|
&& Arg0.getOperand(0).getValueType() == MVT::i1
|
|
|
|
&& (C = dyn_cast<ConstantSDNode>(Arg1))
|
|
|
|
&& C->isNullValue()
|
|
|
|
&& CCOp == ISD::SETNE) {
|
|
|
|
return SimplifySetCC(VT, Arg0.getOperand(0),
|
|
|
|
DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return SDValue();
|
|
|
|
}
|
2013-02-26 17:52:16 +00:00
|
|
|
|
2013-02-26 17:52:23 +00:00
|
|
|
/// \brief Test if RegClass is one of the VSrc classes
|
|
|
|
static bool isVSrc(unsigned RegClass) {
|
|
|
|
return AMDGPU::VSrc_32RegClassID == RegClass ||
|
|
|
|
AMDGPU::VSrc_64RegClassID == RegClass;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Test if RegClass is one of the SSrc classes
|
|
|
|
static bool isSSrc(unsigned RegClass) {
|
|
|
|
return AMDGPU::SSrc_32RegClassID == RegClass ||
|
|
|
|
AMDGPU::SSrc_64RegClassID == RegClass;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Analyze the possible immediate value Op
|
|
|
|
///
|
|
|
|
/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
|
|
|
|
/// and the immediate value if it's a literal immediate
|
|
|
|
int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
|
|
|
|
|
|
|
|
union {
|
|
|
|
int32_t I;
|
|
|
|
float F;
|
|
|
|
} Imm;
|
|
|
|
|
|
|
|
if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N))
|
|
|
|
Imm.I = Node->getSExtValue();
|
|
|
|
else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
|
|
|
|
Imm.F = Node->getValueAPF().convertToFloat();
|
|
|
|
else
|
|
|
|
return -1; // It isn't an immediate
|
|
|
|
|
|
|
|
if ((Imm.I >= -16 && Imm.I <= 64) ||
|
|
|
|
Imm.F == 0.5f || Imm.F == -0.5f ||
|
|
|
|
Imm.F == 1.0f || Imm.F == -1.0f ||
|
|
|
|
Imm.F == 2.0f || Imm.F == -2.0f ||
|
|
|
|
Imm.F == 4.0f || Imm.F == -4.0f)
|
|
|
|
return 0; // It's an inline immediate
|
|
|
|
|
|
|
|
return Imm.I; // It's a literal immediate
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Try to fold an immediate directly into an instruction
|
|
|
|
bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
|
|
|
|
bool &ScalarSlotUsed) const {
|
|
|
|
|
|
|
|
MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
|
|
|
|
if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
const SDValue &Op = Mov->getOperand(0);
|
|
|
|
int32_t Value = analyzeImmediate(Op.getNode());
|
|
|
|
if (Value == -1) {
|
|
|
|
// Not an immediate at all
|
|
|
|
return false;
|
|
|
|
|
|
|
|
} else if (Value == 0) {
|
|
|
|
// Inline immediates can always be fold
|
|
|
|
Operand = Op;
|
|
|
|
return true;
|
|
|
|
|
|
|
|
} else if (Value == Immediate) {
|
|
|
|
// Already fold literal immediate
|
|
|
|
Operand = Op;
|
|
|
|
return true;
|
|
|
|
|
|
|
|
} else if (!ScalarSlotUsed && !Immediate) {
|
|
|
|
// Fold this literal immediate
|
|
|
|
ScalarSlotUsed = true;
|
|
|
|
Immediate = Value;
|
|
|
|
Operand = Op;
|
|
|
|
return true;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Does "Op" fit into register class "RegClass" ?
|
|
|
|
bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op,
|
|
|
|
unsigned RegClass) const {
|
|
|
|
|
|
|
|
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
|
|
|
|
SDNode *Node = Op.getNode();
|
|
|
|
|
2013-03-26 14:04:17 +00:00
|
|
|
const TargetRegisterClass *OpClass;
|
2013-02-26 17:52:23 +00:00
|
|
|
if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
|
|
|
|
const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
|
2013-03-26 14:04:17 +00:00
|
|
|
int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
|
|
|
|
if (OpClassID == -1)
|
|
|
|
OpClass = getRegClassFor(Op.getSimpleValueType());
|
|
|
|
else
|
|
|
|
OpClass = TRI->getRegClass(OpClassID);
|
2013-02-26 17:52:23 +00:00
|
|
|
|
|
|
|
} else if (Node->getOpcode() == ISD::CopyFromReg) {
|
|
|
|
RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode());
|
2013-03-26 14:04:17 +00:00
|
|
|
OpClass = MRI.getRegClass(Reg->getReg());
|
2013-02-26 17:52:23 +00:00
|
|
|
|
|
|
|
} else
|
|
|
|
return false;
|
|
|
|
|
2013-03-26 14:04:17 +00:00
|
|
|
return TRI->getRegClass(RegClass)->hasSubClassEq(OpClass);
|
2013-02-26 17:52:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// \brief Make sure that we don't exeed the number of allowed scalars
|
|
|
|
void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
|
|
|
|
unsigned RegClass,
|
|
|
|
bool &ScalarSlotUsed) const {
|
|
|
|
|
|
|
|
// First map the operands register class to a destination class
|
|
|
|
if (RegClass == AMDGPU::VSrc_32RegClassID)
|
|
|
|
RegClass = AMDGPU::VReg_32RegClassID;
|
|
|
|
else if (RegClass == AMDGPU::VSrc_64RegClassID)
|
|
|
|
RegClass = AMDGPU::VReg_64RegClassID;
|
|
|
|
else
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Nothing todo if they fit naturaly
|
|
|
|
if (fitsRegClass(DAG, Operand, RegClass))
|
|
|
|
return;
|
|
|
|
|
|
|
|
// If the scalar slot isn't used yet use it now
|
|
|
|
if (!ScalarSlotUsed) {
|
|
|
|
ScalarSlotUsed = true;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// This is a conservative aproach, it is possible that we can't determine
|
|
|
|
// the correct register class and copy too often, but better save than sorry.
|
|
|
|
SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
|
|
|
|
SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DebugLoc(),
|
|
|
|
Operand.getValueType(), Operand, RC);
|
|
|
|
Operand = SDValue(Node, 0);
|
|
|
|
}
|
|
|
|
|
2013-02-26 17:52:16 +00:00
|
|
|
SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
|
|
|
|
SelectionDAG &DAG) const {
|
2013-02-26 17:52:23 +00:00
|
|
|
|
|
|
|
// Original encoding (either e32 or e64)
|
|
|
|
int Opcode = Node->getMachineOpcode();
|
|
|
|
const MCInstrDesc *Desc = &TII->get(Opcode);
|
|
|
|
|
|
|
|
unsigned NumDefs = Desc->getNumDefs();
|
|
|
|
unsigned NumOps = Desc->getNumOperands();
|
|
|
|
|
2013-02-26 17:52:47 +00:00
|
|
|
// e64 version if available, -1 otherwise
|
|
|
|
int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
|
|
|
|
const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
|
|
|
|
|
|
|
|
assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
|
|
|
|
assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
|
|
|
|
|
2013-02-26 17:52:23 +00:00
|
|
|
int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
|
|
|
|
bool HaveVSrc = false, HaveSSrc = false;
|
|
|
|
|
|
|
|
// First figure out what we alread have in this instruction
|
|
|
|
for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
|
|
|
|
i != e && Op < NumOps; ++i, ++Op) {
|
|
|
|
|
|
|
|
unsigned RegClass = Desc->OpInfo[Op].RegClass;
|
|
|
|
if (isVSrc(RegClass))
|
|
|
|
HaveVSrc = true;
|
|
|
|
else if (isSSrc(RegClass))
|
|
|
|
HaveSSrc = true;
|
|
|
|
else
|
|
|
|
continue;
|
|
|
|
|
|
|
|
int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
|
|
|
|
if (Imm != -1 && Imm != 0) {
|
|
|
|
// Literal immediate
|
|
|
|
Immediate = Imm;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If we neither have VSrc nor SSrc it makes no sense to continue
|
|
|
|
if (!HaveVSrc && !HaveSSrc)
|
|
|
|
return Node;
|
|
|
|
|
|
|
|
// No scalar allowed when we have both VSrc and SSrc
|
|
|
|
bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
|
|
|
|
|
|
|
|
// Second go over the operands and try to fold them
|
|
|
|
std::vector<SDValue> Ops;
|
2013-02-26 17:52:47 +00:00
|
|
|
bool Promote2e64 = false;
|
2013-02-26 17:52:23 +00:00
|
|
|
for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
|
|
|
|
i != e && Op < NumOps; ++i, ++Op) {
|
|
|
|
|
|
|
|
const SDValue &Operand = Node->getOperand(i);
|
|
|
|
Ops.push_back(Operand);
|
|
|
|
|
|
|
|
// Already folded immediate ?
|
|
|
|
if (isa<ConstantSDNode>(Operand.getNode()) ||
|
|
|
|
isa<ConstantFPSDNode>(Operand.getNode()))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Is this a VSrc or SSrc operand ?
|
|
|
|
unsigned RegClass = Desc->OpInfo[Op].RegClass;
|
2013-03-26 14:04:17 +00:00
|
|
|
if (isVSrc(RegClass) || isSSrc(RegClass)) {
|
|
|
|
// Try to fold the immediates
|
|
|
|
if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
|
|
|
|
// Folding didn't worked, make sure we don't hit the SReg limit
|
|
|
|
ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
2013-02-26 17:52:36 +00:00
|
|
|
|
2013-03-26 14:04:17 +00:00
|
|
|
if (i == 1 && Desc->isCommutable() &&
|
|
|
|
fitsRegClass(DAG, Ops[0], RegClass)) {
|
2013-02-26 17:52:36 +00:00
|
|
|
|
2013-03-26 14:04:17 +00:00
|
|
|
unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
|
|
|
|
assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
|
|
|
|
|
|
|
|
// Test if it makes sense to swap operands
|
|
|
|
if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
|
|
|
|
(!fitsRegClass(DAG, Ops[1], RegClass) &&
|
|
|
|
fitsRegClass(DAG, Ops[1], OtherRegClass))) {
|
2013-02-26 17:52:36 +00:00
|
|
|
|
|
|
|
// Swap commutable operands
|
|
|
|
SDValue Tmp = Ops[1];
|
|
|
|
Ops[1] = Ops[0];
|
|
|
|
Ops[0] = Tmp;
|
2013-03-26 14:04:17 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
2013-02-26 17:52:47 +00:00
|
|
|
|
2013-03-26 14:04:17 +00:00
|
|
|
if (DescE64 && !Immediate) {
|
2013-02-26 17:52:47 +00:00
|
|
|
|
2013-03-26 14:04:17 +00:00
|
|
|
// Test if it makes sense to switch to e64 encoding
|
|
|
|
unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
|
|
|
|
if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
|
|
|
|
continue;
|
2013-02-26 17:52:47 +00:00
|
|
|
|
2013-03-26 14:04:17 +00:00
|
|
|
int32_t TmpImm = -1;
|
|
|
|
if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
|
|
|
|
(!fitsRegClass(DAG, Ops[i], RegClass) &&
|
|
|
|
fitsRegClass(DAG, Ops[1], OtherRegClass))) {
|
2013-02-26 17:52:23 +00:00
|
|
|
|
2013-03-26 14:04:17 +00:00
|
|
|
// Switch to e64 encoding
|
|
|
|
Immediate = -1;
|
|
|
|
Promote2e64 = true;
|
|
|
|
Desc = DescE64;
|
|
|
|
DescE64 = 0;
|
|
|
|
}
|
2013-02-26 17:52:23 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-02-26 17:52:47 +00:00
|
|
|
if (Promote2e64) {
|
|
|
|
// Add the modifier flags while promoting
|
|
|
|
for (unsigned i = 0; i < 4; ++i)
|
|
|
|
Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
|
|
|
|
}
|
|
|
|
|
2013-02-26 17:52:23 +00:00
|
|
|
// Add optional chain and glue
|
|
|
|
for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
|
|
|
|
Ops.push_back(Node->getOperand(i));
|
|
|
|
|
2013-02-26 17:52:47 +00:00
|
|
|
// Either create a complete new or update the current instruction
|
|
|
|
if (Promote2e64)
|
|
|
|
return DAG.getMachineNode(OpcodeE64, Node->getDebugLoc(),
|
|
|
|
Node->getVTList(), Ops.data(), Ops.size());
|
|
|
|
else
|
|
|
|
return DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
|
2013-02-26 17:52:16 +00:00
|
|
|
}
|