llvm-6502/test/MC/Disassembler/AArch64/a64-ignored-fields.txt

# RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s
# RUN: llvm-mc -triple=arm64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s

# The "Rm" bits are ignored, but the canonical representation has them filled
# with 0s. This is what we should produce even if the input bit-pattern had
# something else there.

# CHECK: fcmp    s31, #0.0               // encoding: [0xe8,0x23,0x20,0x1e]
0xe8 0x23 0x33 0x1e
[AArch64] Make the use of FP instructions optional, but enabled by default. This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8 2013-10-31 09:32:11 +00:00			`# RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s \| FileCheck %s`
AArch64/ARM64: port basic disassembly tests to ARM64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207753 91177308-0d34-0410-b5e6-96231b3b80d8 2014-05-01 12:29:56 +00:00			`# RUN: llvm-mc -triple=arm64 -mattr=fp-armv8 -disassemble -show-encoding < %s \| FileCheck %s`
AArch64: remove post-encoder method from FCMP (immediate) instructions. The work done by the post-encoder (setting architecturally unused bits to 0 as required) can be done by the existing operand that covers the "#0.0". This removes at least one use of the discouraged PostEncoderMethod uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176261 91177308-0d34-0410-b5e6-96231b3b80d8 2013-02-28 14:46:14 +00:00
			`# The "Rm" bits are ignored, but the canonical representation has them filled`
			`# with 0s. This is what we should produce even if the input bit-pattern had`
			`# something else there.`

			`# CHECK: fcmp s31, #0.0 // encoding: [0xe8,0x23,0x20,0x1e]`
			`0xe8 0x23 0x33 0x1e`