2014-04-03 16:01:44 +00:00
|
|
|
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \
|
|
|
|
; RUN: | FileCheck %s
|
|
|
|
|
2010-07-08 02:08:50 +00:00
|
|
|
; rdar://7461510
|
2012-03-01 23:27:13 +00:00
|
|
|
; rdar://10964603
|
2010-07-08 02:08:50 +00:00
|
|
|
|
2012-03-01 23:27:13 +00:00
|
|
|
; Disable this optimization unless we know one of them is zero.
|
2010-07-08 02:08:50 +00:00
|
|
|
define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
|
|
|
|
entry:
|
2013-07-14 06:24:09 +00:00
|
|
|
; CHECK-LABEL: t1:
|
2012-03-03 00:26:30 +00:00
|
|
|
; CHECK: vldr [[S0:s[0-9]+]],
|
|
|
|
; CHECK: vldr [[S1:s[0-9]+]],
|
|
|
|
; CHECK: vcmpe.f32 [[S1]], [[S0]]
|
2012-03-15 21:34:14 +00:00
|
|
|
; CHECK: vmrs APSR_nzcv, fpscr
|
2012-03-01 23:27:13 +00:00
|
|
|
; CHECK: beq
|
2010-07-08 02:08:50 +00:00
|
|
|
%0 = load float* %a
|
|
|
|
%1 = load float* %b
|
|
|
|
%2 = fcmp une float %0, %1
|
|
|
|
br i1 %2, label %bb1, label %bb2
|
|
|
|
|
|
|
|
bb1:
|
|
|
|
%3 = call i32 @bar()
|
|
|
|
ret i32 %3
|
|
|
|
|
|
|
|
bb2:
|
|
|
|
%4 = call i32 @foo()
|
|
|
|
ret i32 %4
|
|
|
|
}
|
|
|
|
|
2012-03-01 23:27:13 +00:00
|
|
|
; If one side is zero, the other size sign bit is masked off to allow
|
|
|
|
; +0.0 == -0.0
|
2010-07-13 19:27:42 +00:00
|
|
|
define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
|
|
|
|
entry:
|
2013-07-14 06:24:09 +00:00
|
|
|
; CHECK-LABEL: t2:
|
2012-03-01 23:27:13 +00:00
|
|
|
; CHECK-NOT: vldr
|
2013-07-25 18:35:14 +00:00
|
|
|
; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
|
2012-03-01 23:27:13 +00:00
|
|
|
; CHECK-NOT: b LBB
|
|
|
|
; CHECK: bfc [[REG2]], #31, #1
|
2013-07-25 18:35:14 +00:00
|
|
|
; CHECK: cmp [[REG1]], #0
|
2012-03-01 23:27:13 +00:00
|
|
|
; CHECK: cmpeq [[REG2]], #0
|
|
|
|
; CHECK-NOT: vcmpe.f32
|
|
|
|
; CHECK-NOT: vmrs
|
|
|
|
; CHECK: bne
|
2010-07-13 19:27:42 +00:00
|
|
|
%0 = load double* %a
|
|
|
|
%1 = fcmp oeq double %0, 0.000000e+00
|
|
|
|
br i1 %1, label %bb1, label %bb2
|
|
|
|
|
|
|
|
bb1:
|
|
|
|
%2 = call i32 @bar()
|
|
|
|
ret i32 %2
|
|
|
|
|
|
|
|
bb2:
|
|
|
|
%3 = call i32 @foo()
|
|
|
|
ret i32 %3
|
|
|
|
}
|
|
|
|
|
|
|
|
define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
|
|
|
|
entry:
|
2013-07-14 06:24:09 +00:00
|
|
|
; CHECK-LABEL: t3:
|
2012-03-01 23:27:13 +00:00
|
|
|
; CHECK-NOT: vldr
|
|
|
|
; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
|
|
|
|
; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
|
|
|
|
; CHECK: tst [[REG3]], [[REG4]]
|
|
|
|
; CHECK-NOT: vcmpe.f32
|
|
|
|
; CHECK-NOT: vmrs
|
|
|
|
; CHECK: bne
|
2010-07-13 19:27:42 +00:00
|
|
|
%0 = load float* %a
|
|
|
|
%1 = fcmp oeq float %0, 0.000000e+00
|
|
|
|
br i1 %1, label %bb1, label %bb2
|
|
|
|
|
|
|
|
bb1:
|
|
|
|
%2 = call i32 @bar()
|
|
|
|
ret i32 %2
|
|
|
|
|
|
|
|
bb2:
|
|
|
|
%3 = call i32 @foo()
|
|
|
|
ret i32 %3
|
|
|
|
}
|
|
|
|
|
2010-07-08 02:08:50 +00:00
|
|
|
declare i32 @bar()
|
|
|
|
declare i32 @foo()
|