2007-06-06 07:42:06 +00:00
|
|
|
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-06-06 07:42:06 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// Implements the info about Mips target spec.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#include "Mips.h"
|
2009-08-22 20:48:53 +00:00
|
|
|
#include "MipsMCAsmInfo.h"
|
2007-06-06 07:42:06 +00:00
|
|
|
#include "MipsTargetMachine.h"
|
|
|
|
#include "llvm/PassManager.h"
|
2009-07-25 06:49:55 +00:00
|
|
|
#include "llvm/Target/TargetRegistry.h"
|
2007-06-06 07:42:06 +00:00
|
|
|
using namespace llvm;
|
|
|
|
|
2009-07-25 06:49:55 +00:00
|
|
|
extern "C" void LLVMInitializeMipsTarget() {
|
|
|
|
// Register the target.
|
2009-08-03 02:22:28 +00:00
|
|
|
RegisterTargetMachine<MipsTargetMachine> X(TheMipsTarget);
|
|
|
|
RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
|
2010-01-20 06:34:14 +00:00
|
|
|
RegisterAsmInfo<MipsMCAsmInfo> A(TheMipsTarget);
|
|
|
|
RegisterAsmInfo<MipsMCAsmInfo> B(TheMipselTarget);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
|
2007-08-28 05:13:42 +00:00
|
|
|
// The stack is always 8 byte aligned
|
|
|
|
// On function prologue, the stack is created by decrementing
|
|
|
|
// its pointer. Once decremented, all references are done with positive
|
2008-08-06 06:14:43 +00:00
|
|
|
// offset from the stack/frame pointer, using StackGrowsUp enables
|
|
|
|
// an easier handling.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// Using CodeModel::Large enables different CALL behavior.
|
2007-06-06 07:42:06 +00:00
|
|
|
MipsTargetMachine::
|
2009-08-03 02:22:28 +00:00
|
|
|
MipsTargetMachine(const Target &T, const std::string &TT, const std::string &FS,
|
2009-07-15 20:24:03 +00:00
|
|
|
bool isLittle=false):
|
2009-08-11 20:42:37 +00:00
|
|
|
LLVMTargetMachine(T, TT),
|
2009-08-03 02:22:28 +00:00
|
|
|
Subtarget(TT, FS, isLittle),
|
2009-11-07 19:07:32 +00:00
|
|
|
DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-n32") :
|
|
|
|
std::string("E-p:32:32:32-i8:8:32-i16:16:32-n32")),
|
2008-06-04 01:45:25 +00:00
|
|
|
InstrInfo(*this),
|
|
|
|
FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0),
|
2009-08-11 20:42:37 +00:00
|
|
|
TLInfo(*this) {
|
2008-07-14 14:42:54 +00:00
|
|
|
// Abicall enables PIC by default
|
2009-08-03 02:22:28 +00:00
|
|
|
if (getRelocationModel() == Reloc::Default) {
|
|
|
|
if (Subtarget.isABI_O32())
|
|
|
|
setRelocationModel(Reloc::PIC_);
|
|
|
|
else
|
|
|
|
setRelocationModel(Reloc::Static);
|
|
|
|
}
|
2007-10-09 03:01:19 +00:00
|
|
|
}
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2008-06-04 01:45:25 +00:00
|
|
|
MipselTargetMachine::
|
2009-08-03 02:22:28 +00:00
|
|
|
MipselTargetMachine(const Target &T, const std::string &TT,
|
|
|
|
const std::string &FS) :
|
|
|
|
MipsTargetMachine(T, TT, FS, true) {}
|
2008-06-04 01:45:25 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Install an instruction selector pass using
|
|
|
|
// the ISelDag to gen Mips code.
|
|
|
|
bool MipsTargetMachine::
|
2010-01-20 06:34:14 +00:00
|
|
|
addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
|
|
|
|
{
|
2007-06-06 07:42:06 +00:00
|
|
|
PM.add(createMipsISelDag(*this));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Implemented by targets that want to run passes immediately before
|
|
|
|
// machine code is emitted. return true if -print-machineinstrs should
|
|
|
|
// print out the code after the passes.
|
|
|
|
bool MipsTargetMachine::
|
2009-04-29 23:29:43 +00:00
|
|
|
addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
|
2007-06-06 07:42:06 +00:00
|
|
|
{
|
2007-08-18 01:58:15 +00:00
|
|
|
PM.add(createMipsDelaySlotFillerPass(*this));
|
|
|
|
return true;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|