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llvm-6502/test/CodeGen/Mips/msa/basic_operations_float.ll

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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 10:08:31 +00:00
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test. Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 11:04:16 +00:00
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
@v2f64 = global <2 x double> <double 0.0, double 0.0>
[mips][msa] Fix element extraction where the index is variable. Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 13:31:37 +00:00
@i32 = global i32 0
[mips][msa] Added support for build_vector for v4f32 and v2f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 13:14:41 +00:00
@f32 = global float 0.0
@f64 = global double 0.0
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
define void @const_v4f32() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: const_v4f32:
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
[mips][msa] Added support for build_vector for v4f32 and v2f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 13:14:41 +00:00
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
[mips][msa] Added support for build_vector for v4f32 and v2f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 13:14:41 +00:00
; MIPS32: lui [[R1:\$[0-9]+]], 16256
; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]]
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
[mips][msa] Added support for build_vector for v4f32 and v2f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 13:14:41 +00:00
; MIPS32: lui [[R1:\$[0-9]+]], 18304
; MIPS32: ori [[R2:\$[0-9]+]], [[R1]], 128
; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]]
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
ret void
; MIPS32: .size const_v4f32
}
define void @const_v2f64() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: const_v2f64:
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
[mips][msa] Added support for build_vector for v4f32 and v2f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 13:14:41 +00:00
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 12:02:46 +00:00
ret void
; MIPS32: .size const_v2f64
}
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:17:32 +00:00
[mips][msa] Added support for build_vector for v4f32 and v2f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 13:14:41 +00:00
define void @nonconst_v4f32() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: nonconst_v4f32:
[mips][msa] Added support for build_vector for v4f32 and v2f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 13:14:41 +00:00
%1 = load float *@f32
%2 = insertelement <4 x float> undef, float %1, i32 0
%3 = insertelement <4 x float> %2, float %1, i32 1
%4 = insertelement <4 x float> %3, float %1, i32 2
%5 = insertelement <4 x float> %4, float %1, i32 3
store volatile <4 x float> %5, <4 x float>*@v4f32
; MIPS32: lwc1 $f[[R1:[0-9]+]], 0(
; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]]
ret void
; MIPS32: .size nonconst_v4f32
}
define void @nonconst_v2f64() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: nonconst_v2f64:
[mips][msa] Added support for build_vector for v4f32 and v2f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15 13:14:41 +00:00
%1 = load double *@f64
%2 = insertelement <2 x double> undef, double %1, i32 0
%3 = insertelement <2 x double> %2, double %1, i32 1
store volatile <2 x double> %3, <2 x double>*@v2f64
; MIPS32: ldc1 $f[[R1:[0-9]+]], 0(
; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]]
ret void
; MIPS32: .size nonconst_v2f64
}
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:17:32 +00:00
define float @extract_v4f32() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: extract_v4f32:
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:17:32 +00:00
%1 = load <4 x float>* @v4f32
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = fadd <4 x float> %1, %1
; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <4 x float> %2, i32 1
; Element 1 can be obtained by splatting it across the vector and extracting
; $w0:sub_lo
; MIPS32-DAG: splati.w $w0, [[R1]][1]
ret float %3
; MIPS32: .size extract_v4f32
}
define float @extract_v4f32_elt0() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: extract_v4f32_elt0:
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:17:32 +00:00
%1 = load <4 x float>* @v4f32
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = fadd <4 x float> %1, %1
; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
%3 = extractelement <4 x float> %2, i32 0
; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
; MIPS32-NOT: copy_u.w
; MIPS32-NOT: mtc1
ret float %3
; MIPS32: .size extract_v4f32_elt0
}
[mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3. Summary: Previously, attempting to extract lanes 2 and 3 would actually extract lane 1. The MSA CodeGen tests only covered lanes 0 and 1. Differential Revision: http://llvm-reviews.chandlerc.com/D2935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202848 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 13:54:30 +00:00
define float @extract_v4f32_elt2() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: extract_v4f32_elt2:
[mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3. Summary: Previously, attempting to extract lanes 2 and 3 would actually extract lane 1. The MSA CodeGen tests only covered lanes 0 and 1. Differential Revision: http://llvm-reviews.chandlerc.com/D2935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202848 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 13:54:30 +00:00
%1 = load <4 x float>* @v4f32
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = fadd <4 x float> %1, %1
; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <4 x float> %2, i32 2
; Element 2 can be obtained by splatting it across the vector and extracting
; $w0:sub_lo
; MIPS32-DAG: splati.w $w0, [[R1]][2]
ret float %3
; MIPS32: .size extract_v4f32_elt2
}
[mips][msa] Fix element extraction where the index is variable. Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 13:31:37 +00:00
define float @extract_v4f32_vidx() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: extract_v4f32_vidx:
[mips][msa] Fix element extraction where the index is variable. Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 13:31:37 +00:00
%1 = load <4 x float>* @v4f32
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = fadd <4 x float> %1, %1
; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32* @i32
; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <4 x float> %2, i32 %3
; MIPS32-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
ret float %4
; MIPS32: .size extract_v4f32_vidx
}
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:17:32 +00:00
define double @extract_v2f64() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: extract_v2f64:
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:17:32 +00:00
%1 = load <2 x double>* @v2f64
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
%2 = fadd <2 x double> %1, %1
; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = extractelement <2 x double> %2, i32 1
; Element 1 can be obtained by splatting it across the vector and extracting
; $w0:sub_64
; MIPS32-DAG: splati.d $w0, [[R1]][1]
; MIPS32-NOT: copy_u.w
; MIPS32-NOT: mtc1
; MIPS32-NOT: mthc1
; MIPS32-NOT: sll
; MIPS32-NOT: sra
ret double %3
; MIPS32: .size extract_v2f64
}
define double @extract_v2f64_elt0() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: extract_v2f64_elt0:
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:17:32 +00:00
%1 = load <2 x double>* @v2f64
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
%2 = fadd <2 x double> %1, %1
; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
%3 = extractelement <2 x double> %2, i32 0
; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
; MIPS32-NOT: copy_u.w
; MIPS32-NOT: mtc1
; MIPS32-NOT: mthc1
; MIPS32-NOT: sll
; MIPS32-NOT: sra
ret double %3
; MIPS32: .size extract_v2f64_elt0
}
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:31:32 +00:00
[mips][msa] Fix element extraction where the index is variable. Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 13:31:37 +00:00
define double @extract_v2f64_vidx() nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: extract_v2f64_vidx:
[mips][msa] Fix element extraction where the index is variable. Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 13:31:37 +00:00
%1 = load <2 x double>* @v2f64
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = fadd <2 x double> %1, %1
; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
%3 = load i32* @i32
; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%4 = extractelement <2 x double> %2, i32 %3
; MIPS32-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
ret double %4
; MIPS32: .size extract_v2f64_vidx
}
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:31:32 +00:00
define void @insert_v4f32(float %a) nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: insert_v4f32:
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:31:32 +00:00
%1 = load <4 x float>* @v4f32
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
%2 = insertelement <4 x float> %1, float %a, i32 1
; float argument passed in $f12
; MIPS32-DAG: insve.w [[R1]][1], $w12[0]
store <4 x float> %2, <4 x float>* @v4f32
; MIPS32-DAG: st.w [[R1]]
ret void
; MIPS32: .size insert_v4f32
}
define void @insert_v2f64(double %a) nounwind {
[mips][msa] Use CHECK-LABEL in basic_operations*.ll Differential Revision: http://reviews.llvm.org/D3536 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 14:28:58 +00:00
; MIPS32-LABEL: insert_v2f64:
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 12:31:32 +00:00
%1 = load <2 x double>* @v2f64
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
%2 = insertelement <2 x double> %1, double %a, i32 1
; double argument passed in $f12
; MIPS32-DAG: insve.d [[R1]][1], $w12[0]
store <2 x double> %2, <2 x double>* @v2f64
; MIPS32-DAG: st.d [[R1]]
ret void
; MIPS32: .size insert_v2f64
}
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207640 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 12:09:32 +00:00
define void @insert_v4f32_vidx(float %a) nounwind {
; MIPS32-LABEL: insert_v4f32_vidx:
%1 = load <4 x float>* @v4f32
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = load i32* @i32
; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%3 = insertelement <4 x float> %1, float %a, i32 %2
; float argument passed in $f12
; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
; MIPS32-DAG: insve.w [[R1]][0], $w12[0]
; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
store <4 x float> %3, <4 x float>* @v4f32
; MIPS32-DAG: st.w [[R1]]
ret void
; MIPS32: .size insert_v4f32_vidx
}
define void @insert_v2f64_vidx(double %a) nounwind {
; MIPS32-LABEL: insert_v2f64_vidx:
%1 = load <2 x double>* @v2f64
; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
%2 = load i32* @i32
; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
%3 = insertelement <2 x double> %1, double %a, i32 %2
; double argument passed in $f12
; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
; MIPS32-DAG: insve.d [[R1]][0], $w12[0]
; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
store <2 x double> %3, <2 x double>* @v2f64
; MIPS32-DAG: st.d [[R1]]
ret void
; MIPS32: .size insert_v2f64_vidx
}
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