llvm-6502/test/MC/ARM/directive-fpu-instrs.s

// RUN: llvm-mc -triple armv7-unknown-linux-gnueabi -mattr=+vfp3,-neon %s

.fpu neon
VAND d3, d5, d5
vldr d21, [r7, #296]

@ .thumb should not disable the prior .fpu neon
.thumb

vmov q4, q11 @ v4si
str r6, [r7, #264]
mov r6, r5
vldr d21, [r7, #296]
add r9, r7, #216

fstmfdd sp!, {d8, d9, d10, d11, d12, d13, d14, d15}
[ARM] Honor FeatureD16 in the assembler and disassembler Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221341 91177308-0d34-0410-b5e6-96231b3b80d8 2014-11-05 12:06:39 +00:00			`// RUN: llvm-mc -triple armv7-unknown-linux-gnueabi -mattr=+vfp3,-neon %s`
arm asm: Let .fpu enable instructions, PR20447. I'm not very happy with duplicating the fpu->feature mapping in ARMAsmParser.cpp and in clang's driver. See the bug for a patch that doesn't do that, and the review thread [1] for why this duplication exists. 1: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140811/231052.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215811 91177308-0d34-0410-b5e6-96231b3b80d8 2014-08-16 05:37:51 +00:00
			`.fpu neon`
			`VAND d3, d5, d5`
			`vldr d21, [r7, #296]`

			`@ .thumb should not disable the prior .fpu neon`
			`.thumb`

			`vmov q4, q11 @ v4si`
			`str r6, [r7, #264]`
			`mov r6, r5`
			`vldr d21, [r7, #296]`
			`add r9, r7, #216`

			`fstmfdd sp!, {d8, d9, d10, d11, d12, d13, d14, d15}`