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llvm-6502/lib/Target/X86/Makefile

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We know exactly what the value of $< is, so instead of using `basename $<` to get just the filename and not the full path, just use the filename directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9730 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-05 06:43:36 +00:00
##===- lib/Target/X86/Makefile -----------------------------*- Makefile -*-===##
Added LLVM copyright notice to Makefiles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9312 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-20 22:26:57 +00:00
#
# The LLVM Compiler Infrastructure
#
# This file was developed by the LLVM research group and is distributed under
# the University of Illinois Open Source License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
Initial checkin of X86 backend. We can instruction select exactly one instruction 'ret void'. Wow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
2002-10-25 22:55:53 +00:00
LEVEL = ../../..
LIBRARYNAME = x86
include $(LEVEL)/Makefile.common
Factor a bunch of the rules and add support for generating the asmwriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 06:01:32 +00:00
TARGET = X86
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
# Make sure that tblgen is run, first thing.
Start using tablegenerated instruction descriptions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7538 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:59 +00:00
$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
X86GenRegisterInfo.inc X86GenInstrNames.inc \
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-03 20:36:57 +00:00
X86GenInstrInfo.inc X86GenATTAsmWriter.inc \
X86GenIntelAsmWriter.inc
Factor a bunch of the rules and add support for generating the asmwriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 06:01:32 +00:00
TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
$(SourceDir)/../Target.td
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Factor a bunch of the rules and add support for generating the asmwriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 06:01:32 +00:00
$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td register names with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Factor a bunch of the rules and add support for generating the asmwriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 06:01:32 +00:00
$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td register information header with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Factor a bunch of the rules and add support for generating the asmwriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 06:01:32 +00:00
$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td register info implementation with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
Factor a bunch of the rules and add support for generating the asmwriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 06:01:32 +00:00
$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td instruction names with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
Start using tablegenerated instruction descriptions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7538 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:54:59 +00:00
Factor a bunch of the rules and add support for generating the asmwriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 06:01:32 +00:00
$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td instruction information with tblgen"
Be a little more specific about what is begin generated. Only print command line if VERBOSE=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
2003-09-10 19:52:54 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
Add support for a pattern matching instruction selector. This is still in the early implementation phases, so it is disabled by default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7719 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-11 14:59:22 +00:00
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-03 20:36:57 +00:00
$(TARGET)GenATTAsmWriter.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td AT&T assembly writer with tblgen"
Factor a bunch of the rules and add support for generating the asmwriter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-01 06:01:32 +00:00
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
Tablgen files for really simple instruction selector git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12714 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-06 19:34:00 +00:00
Add support for the -x86-asm-syntax flag, which can be used to choose between Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-03 20:36:57 +00:00
$(TARGET)GenIntelAsmWriter.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td Intel assembly writer with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -asmwriternum=1 -o $@
Disable the pattern isel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15787 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-15 23:02:17 +00:00
#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
# @echo "Building $(TARGET).td instruction selector with tblgen"
# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
Tablgen files for really simple instruction selector git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12714 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-06 19:34:00 +00:00
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 15:48:14 +00:00
clean::
$(VERB) rm -f *.inc
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