2012-02-18 12:03:15 +00:00
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//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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2012-02-18 12:03:15 +00:00
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#ifndef POWERPC_INSTRUCTIONINFO_H
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#define POWERPC_INSTRUCTIONINFO_H
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2004-08-17 04:55:41 +00:00
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2005-10-14 23:51:18 +00:00
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#include "PPC.h"
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2005-10-14 23:59:06 +00:00
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#include "PPCRegisterInfo.h"
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2012-03-17 18:46:09 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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2011-07-01 17:57:27 +00:00
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#define GET_INSTRINFO_HEADER
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#include "PPCGenInstrInfo.inc"
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namespace llvm {
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/// PPCII - This namespace holds all of the PowerPC target-specific
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/// per-instruction flags. These must match the corresponding definitions in
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/// PPC.td and PPCInstrFormats.td.
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namespace PPCII {
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enum {
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// PPC970 Instruction Flags. These flags describe the characteristics of the
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// PowerPC 970 (aka G5) dispatch groups and how they are formed out of
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// raw machine instructions.
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/// PPC970_First - This instruction starts a new dispatch group, so it will
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/// always be the first one in the group.
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PPC970_First = 0x1,
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/// PPC970_Single - This instruction starts a new dispatch group and
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/// terminates it, so it will be the sole instruction in the group.
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PPC970_Single = 0x2,
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2006-03-13 05:15:10 +00:00
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/// PPC970_Cracked - This instruction is cracked into two pieces, requiring
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/// two dispatch pipes to be available to issue.
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PPC970_Cracked = 0x4,
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/// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
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/// an instruction is issued to.
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PPC970_Shift = 3,
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PPC970_Mask = 0x07 << PPC970_Shift
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};
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enum PPC970_Unit {
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/// These are the various PPC970 execution unit pipelines. Each instruction
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/// is one of these.
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PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
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PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
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PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
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PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
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PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
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PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
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PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
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PPC970_BRU = 7 << PPC970_Shift // Branch Unit
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};
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2010-11-14 23:42:06 +00:00
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} // end namespace PPCII
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2011-07-01 17:57:27 +00:00
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class PPCInstrInfo : public PPCGenInstrInfo {
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PPCTargetMachine &TM;
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const PPCRegisterInfo RI;
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2008-07-07 23:14:23 +00:00
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bool StoreRegToStackSlot(MachineFunction &MF,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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2013-03-17 04:43:44 +00:00
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SmallVectorImpl<MachineInstr*> &NewMIs,
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2013-03-23 22:06:03 +00:00
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bool &NonRI, bool &SpillsVRS) const;
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bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI, bool &SpillsVRS) const;
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public:
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explicit PPCInstrInfo(PPCTargetMachine &TM);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetMachine *TM,
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const ScheduleDAG *DAG) const;
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2011-12-02 04:58:02 +00:00
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ScheduleHazardRecognizer *
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const;
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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2012-06-19 21:14:34 +00:00
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bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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2006-02-02 20:12:32 +00:00
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2005-09-09 18:17:41 +00:00
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// rotate amt is zero. We also have to munge the immediates a bit.
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2008-06-16 07:33:11 +00:00
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virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
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2010-12-24 04:28:06 +00:00
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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2006-10-13 21:21:17 +00:00
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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2009-02-09 07:14:22 +00:00
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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2007-05-18 00:05:48 +00:00
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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2010-06-17 22:43:56 +00:00
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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2013-04-05 23:29:01 +00:00
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// Select analysis.
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virtual bool canInsertSelect(const MachineBasicBlock&,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned, unsigned, int&, int&, int&) const;
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virtual void insertSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned TrueReg, unsigned FalseReg) const;
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2010-07-11 07:31:00 +00:00
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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2010-12-24 04:28:06 +00:00
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2008-01-01 21:11:32 +00:00
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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2010-05-06 19:06:44 +00:00
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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2008-01-01 21:11:32 +00:00
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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2010-05-06 19:06:44 +00:00
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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2010-12-24 04:28:06 +00:00
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2010-04-26 07:39:36 +00:00
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virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
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2010-04-29 01:13:30 +00:00
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int FrameIx,
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2010-04-26 07:39:36 +00:00
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uint64_t Offset,
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const MDNode *MDPtr,
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DebugLoc DL) const;
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2008-08-14 22:49:33 +00:00
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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2010-12-24 04:28:06 +00:00
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2013-04-06 19:30:30 +00:00
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virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const;
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2013-04-09 22:58:37 +00:00
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// If conversion by predication (only supported by some branch instructions).
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// All of the profitability checks always return true; it is always
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// profitable to use the predicated branches.
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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const BranchProbability &Probability) const {
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return true;
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}
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumT, unsigned ExtraT,
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MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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2013-04-10 18:30:16 +00:00
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const BranchProbability &Probability) const;
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2013-04-09 22:58:37 +00:00
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virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles,
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const BranchProbability
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&Probability) const {
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return true;
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}
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virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const {
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return false;
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}
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// Predication support.
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bool isPredicated(const MachineInstr *MI) const;
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virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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virtual bool isPredicable(MachineInstr *MI) const;
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2008-04-16 20:10:13 +00:00
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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///
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virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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};
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}
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#endif
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