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llvm-6502/test/MC/AsmParser/X86/x86_instructions.s

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fix the encoding of sldt GR16 to have the 0x66 prefix, and add sldt GR32, which isn't documented in the intel manual but which gas accepts. Part of rdar://8418316 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:45:10 +00:00
// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s > %t 2> %t.err
MC/X86: Warn on scale factors > 1 without index register, instead of erroring, for 'as' compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 19:13:38 +00:00
// RUN: FileCheck < %t %s
// RUN: FileCheck --check-prefix=CHECK-STDERR < %t.err %s
Add this test back, the check pattern was too strict. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77662 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 03:11:49 +00:00
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: subb %al, %al
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 20:53:16 +00:00
subb %al, %al
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: addl $24, %eax
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 20:53:16 +00:00
addl $24, %eax
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: movl %eax, 10(%ebp)
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 20:53:16 +00:00
movl %eax, 10(%ebp)
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: movl %eax, 10(%ebp,%ebx)
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 20:53:16 +00:00
movl %eax, 10(%ebp, %ebx)
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: movl %eax, 10(%ebp,%ebx,4)
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 20:53:16 +00:00
movl %eax, 10(%ebp, %ebx, 4)
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: movl %eax, 10(,%ebx,4)
llvm-mc/X86: Sketch match functions for immediates and memory operands. Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-31 20:53:16 +00:00
movl %eax, 10(, %ebx, 4)
MC/X86 AsmParser: Handle absolute memory operands correctly. We were doing something totally broken and parsing them as immediates, but the .td file also had the wrong match class so things sortof worked. Except, that is, that we would parse movl $0, %eax as movl 0, %eax Feel free to guess how well that worked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-30 01:02:48 +00:00
// CHECK: movl 0, %eax
movl 0, %eax
// CHECK: movl $0, %eax
movl $0, %eax
Mark EH_RETURN64 as CodeGenOnly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-22 20:16:37 +00:00
// CHECK: ret
ret
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 07:20:21 +00:00
// FIXME: Check that this matches SUB32ri8
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: subl $1, %eax
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 07:20:21 +00:00
subl $1, %eax
// FIXME: Check that this matches SUB32ri8
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: subl $-1, %eax
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 07:20:21 +00:00
subl $-1, %eax
// FIXME: Check that this matches SUB32ri
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: subl $256, %eax
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 07:20:21 +00:00
subl $256, %eax
llvm-mc/AsmParser: Disambiguate i64i8imm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78598 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 21:06:41 +00:00
// FIXME: Check that this matches XOR64ri8
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: xorq $1, %rax
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78636 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 02:59:53 +00:00
xorq $1, %rax
llvm-mc/AsmParser: Implement user defined super classes. - We can now discriminate SUB32ri8 from SUB32ri, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-09 07:20:21 +00:00
llvm-mc/AsmParser: Disambiguate i64i8imm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78598 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 21:06:41 +00:00
// FIXME: Check that this matches XOR64ri32
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: xorq $256, %rax
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78636 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 02:59:53 +00:00
xorq $256, %rax
// FIXME: Check that this matches SUB8rr
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: subb %al, %bl
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78636 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 02:59:53 +00:00
subb %al, %bl
// FIXME: Check that this matches SUB16rr
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: subw %ax, %bx
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78636 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 02:59:53 +00:00
subw %ax, %bx
// FIXME: Check that this matches SUB32rr
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: subl %eax, %ebx
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands. - This drops us to 123 ambiguous instructions (previously ~500) on X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78636 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 02:59:53 +00:00
subl %eax, %ebx
llvm-mc/X86: Parse '*' correctly (in the way the matcher expects). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78642 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 05:00:25 +00:00
// FIXME: Check that this matches the correct instruction.
X86-64: Mark WINCALL and more tail call instructions as code gen only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 07:21:07 +00:00
// CHECK: callq *%rax
llvm-mc/X86: Parse '*' correctly (in the way the matcher expects). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78642 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 05:00:25 +00:00
call *%rax
llvm-mc/AsmParser: Match hard coded registers (e.g. 'shldl %cl, %eax, %eax') We now match all of 403.gcc (as emitted by clang). :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78750 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 23:23:44 +00:00
// FIXME: Check that this matches the correct instruction.
Update llvm-mc / MCAsmStreamer to print the instruction using the actual target specific printer (this only works on x86, for now). - This makes it possible to do some correctness checking of the parsing and matching, since we can compare the results of 'as' on the original input, to those of 'as' on the output from llvm-mc. - In theory, we could now have an easy ATT -> Intel syntax converter. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-14 03:48:55 +00:00
// CHECK: shldl %cl, %eax, %ebx
llvm-mc/AsmParser: Match hard coded registers (e.g. 'shldl %cl, %eax, %eax') We now match all of 403.gcc (as emitted by clang). :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78750 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 23:23:44 +00:00
shldl %cl, %eax, %ebx
AsmParser/X86: Add temporary hack to allow parsing "sal". Eventually we need some mechanism for specifying alternative syntaxes, but I'm not sure what form that should take yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95158 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-02 23:46:47 +00:00
// CHECK: shll $2, %eax
shll $2, %eax
// CHECK: shll $2, %eax
sall $2, %eax
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
// CHECK: rep
// CHECK: insb
rep;insb
// CHECK: rep
// CHECK: outsb
rep;outsb
// CHECK: rep
// CHECK: movsb
rep;movsb
fix rdar://8470918 - llvm-mc can't assemble smovl git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:11:53 +00:00
// rdar://8470918
smovb // CHECK: movsb
smovw // CHECK: movsw
smovl // CHECK: movsl
smovq // CHECK: movsq
fix rdar://8456361 - llvm-mc rejects 'rep movsd' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114526 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 03:50:32 +00:00
// rdar://8456361
// CHECK: rep
// CHECK: movsl
rep movsd
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
// CHECK: rep
// CHECK: lodsb
rep;lodsb
// CHECK: rep
// CHECK: stosb
rep;stosb
// NOTE: repz and repe have the same opcode as rep
// CHECK: rep
// CHECK: cmpsb
repz;cmpsb
// NOTE: repnz has the same opcode as repne
// CHECK: repne
// CHECK: cmpsb
repnz;cmpsb
// NOTE: repe and repz have the same opcode as rep
// CHECK: rep
// CHECK: scasb
repe;scasb
// CHECK: repne
// CHECK: scasb
repne;scasb
// CHECK: lock
MC/X86: Push immediate operands as immediates not expressions when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:17:21 +00:00
// CHECK: cmpxchgb %al, (%ebx)
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
lock;cmpxchgb %al, 0(%ebx)
// CHECK: cs
MC/X86: Push immediate operands as immediates not expressions when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:17:21 +00:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
cs;movb 0(%eax), %al
// CHECK: ss
MC/X86: Push immediate operands as immediates not expressions when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:17:21 +00:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
ss;movb 0(%eax), %al
// CHECK: ds
MC/X86: Push immediate operands as immediates not expressions when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:17:21 +00:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
ds;movb 0(%eax), %al
// CHECK: es
MC/X86: Push immediate operands as immediates not expressions when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:17:21 +00:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
es;movb 0(%eax), %al
// CHECK: fs
MC/X86: Push immediate operands as immediates not expressions when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:17:21 +00:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
fs;movb 0(%eax), %al
// CHECK: gs
MC/X86: Push immediate operands as immediates not expressions when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:17:21 +00:00
// CHECK: movb (%eax), %al
Added support for X86 instruction prefixes so llvm-mc can assemble them. The Lock prefix, Repeat string operation prefixes and the Segment override prefixes. Also added versions of the move string and store string instructions without the repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is happy building the disassembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03 21:04:42 +00:00
gs;movb 0(%eax), %al
Implement x86 asm parsing support for %st and %st(4) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09 00:49:22 +00:00
// CHECK: fadd %st(0)
// CHECK: fadd %st(1)
// CHECK: fadd %st(7)
fadd %st(0)
fadd %st(1)
fadd %st(7)
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. - This fixes "leal 0, %eax", for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 22:39:14 +00:00
// CHECK: leal 0, %eax
leal 0, %eax
fix rdar://7986634 - match instruction opcodes case insensitively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:34:33 +00:00
// rdar://7986634 - Insensitivity on opcodes.
// CHECK: int3
INT3
MC/X86: Warn on scale factors > 1 without index register, instead of erroring, for 'as' compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 19:13:38 +00:00
// Allow scale factor without index register.
// CHECK: movaps %xmm3, (%esi)
// CHECK-STDERR: warning: scale factor without index register is ignored
movaps %xmm3, (%esi, 2)
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 19:24:18 +00:00
// CHECK: imull $12, %eax, %eax
imul $12, %eax
MC/X86: Tweak imul recognition, previous hack only applies for the imul form taking immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 19:37:56 +00:00
// CHECK: imull %ecx, %eax
imull %ecx, %eax
fix the operand constraints of the immediate form of in/out, allowing unsigned 8-bit operands. This fixes rdar://8208481 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 23:29:05 +00:00
// rdar://8208481
// CHECK: outb %al, $161
outb %al, $161
// CHECK: outw %ax, $128
outw %ax, $128
// CHECK: inb $161, %al
inb $161, %al
fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113184 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 23:40:56 +00:00
// rdar://8017621
// CHECK: pushq $1
push $1
"sldt <mem>" is ambiguous in 64-bit mode, but should always be disambiguated as sldtw. sldtw and sldtq with a mem operands have the same effect, but sldtw is more compact. Force it to sldtw, resolving rdar://8017530 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 23:51:44 +00:00
// rdar://8017530
// CHECK: sldtw 4
sldt 4
add missing cmov aliases, this resolves rdar://8208499 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113189 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 00:05:45 +00:00
// rdar://8208499
// CHECK: cmovnew %bx, %ax
cmovnz %bx, %ax
// CHECK: cmovneq %rbx, %rax
cmovnzq %rbx, %rax
implement rdar://8407928 - support for in/out with a missing "a" register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 16:32:12 +00:00
// rdar://8407928
// CHECK: inb $127, %al
// CHECK: inw %dx, %ax
// CHECK: outb %al, $127
// CHECK: outw %ax, %dx
// CHECK: inl %dx, %eax
inb $0x7f
inw %dx
outb $0x7f
outw %dx
inl %dx
add a terrible hack to allow out with dx is parens, a gas bug. This fixes PR8114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 23:34:29 +00:00
// PR8114
// CHECK: outb %al, %dx
// CHECK: outw %ax, %dx
// CHECK: outl %eax, %dx
out %al, (%dx)
out %ax, (%dx)
outl %eax, (%dx)
add a bunch of aliases for fp operations with no operand, rdar://8431422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:04:33 +00:00
// rdar://8431422
// CHECK: fxch %st(1)
// CHECK: fucom %st(1)
// CHECK: fucomp %st(1)
// CHECK: faddp %st(1)
// CHECK: faddp %st(0)
// CHECK: fsubp %st(1)
// CHECK: fsubrp %st(1)
// CHECK: fmulp %st(1)
// CHECK: fdivp %st(1)
// CHECK: fdivrp %st(1)
fxch
fucom
fucomp
faddp
faddp %st
fsubp
fsubrp
fmulp
fdivp
fdivrp
add some aliases for f[u]comi, part of rdar://8431422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:08:38 +00:00
// CHECK: fcomi %st(1), %st(0)
// CHECK: fcomi %st(2), %st(0)
// CHECK: fucomi %st(1), %st(0)
// CHECK: fucomi %st(2), %st(0)
// CHECK: fucomi %st(2), %st(0)
fcomi
fcomi %st(2)
fucomi
fucomi %st(2)
fucomi %st(2), %st
add various broken forms of fnstsw. I didn't add the %rax version because it adds a prefix and makes even less sense than the other broken forms. This wraps up rdar://8431422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:15:16 +00:00
// CHECK: fnstsw %ax
// CHECK: fnstsw %ax
// CHECK: fnstsw %ax
// CHECK: fnstsw %ax
fnstsw
fnstsw %ax
fnstsw %eax
fnstsw %al
fix rdar://8431880 - rcl/rcr with no shift amount not recognized git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:33:27 +00:00
// rdar://8431880
// CHECK: rclb $1, %bl
// CHECK: rcll $1, 3735928559(%ebx,%ecx,8)
// CHECK: rcrl $1, %ecx
// CHECK: rcrl $1, 305419896
rcl %bl
rcll 0xdeadbeef(%ebx,%ecx,8)
rcr %ecx
rcrl 0x12345678
implement aliases for shld/shrd, part of rdar://8418316 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:37:18 +00:00
// rdar://8418316
// CHECK: shldw $1, %bx, %bx
// CHECK: shldw $1, %bx, %bx
// CHECK: shrdw $1, %bx, %bx
// CHECK: shrdw $1, %bx, %bx
shld %bx,%bx
shld $1, %bx,%bx
shrd %bx,%bx
shrd $1, %bx,%bx
fix the encoding of sldt GR16 to have the 0x66 prefix, and add sldt GR32, which isn't documented in the intel manual but which gas accepts. Part of rdar://8418316 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 04:45:10 +00:00
// CHECK: sldtl %ecx
// CHECK: encoding: [0x0f,0x00,0xc1]
// CHECK: sldtw %cx
// CHECK: encoding: [0x66,0x0f,0x00,0xc1]
sldt %ecx
sldt %cx
Disambiguate lcall/ljmp to the 32-bit version. This happens even in 64-bit mode apparently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:14:54 +00:00
// CHECK: lcalll *3135175374
// CHECK: ljmpl *3135175374
lcall *0xbadeface
ljmp *0xbadeface
fix rdar://8444631 - encoder crash on 'enter' What a weird instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:02:29 +00:00
// rdar://8444631
// CHECK: enter $31438, $0
// CHECK: encoding: [0xc8,0xce,0x7a,0x00]
// CHECK: enter $31438, $1
// CHECK: encoding: [0xc8,0xce,0x7a,0x01]
// CHECK: enter $31438, $127
// CHECK: encoding: [0xc8,0xce,0x7a,0x7f]
enter $0x7ace,$0
enter $0x7ace,$1
enter $0x7ace,$0x7f
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp' -This line, and those below, will be ignored-- M test/MC/AsmParser/X86/x86_instructions.s M lib/Target/X86/AsmParser/X86AsmParser.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:04:03 +00:00
// rdar://8456389
// CHECK: fstps (%eax)
implement support for 32-bit address operands in 64-bit mode, which are defined to emit the 0x67 prefix byte. rdar://8482675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 03:33:25 +00:00
// CHECK: encoding: [0x67,0xd9,0x18]
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp' -This line, and those below, will be ignored-- M test/MC/AsmParser/X86/x86_instructions.s M lib/Target/X86/AsmParser/X86AsmParser.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:04:03 +00:00
fstp (%eax)
Fix rdar://8456364 - llvm-mc rejects '%CS' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114528 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:11:10 +00:00
// rdar://8456364
// CHECK: movw %cs, %ax
mov %CS, %ax
add the missing aliases for fp stack cmovs, rdar://8456391 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:56:20 +00:00
// rdar://8456391
fcmovb %st(1), %st(0) // CHECK: fcmovb %st(1), %st(0)
fcmove %st(1), %st(0) // CHECK: fcmove %st(1), %st(0)
fcmovbe %st(1), %st(0) // CHECK: fcmovbe %st(1), %st(0)
fcmovu %st(1), %st(0) // CHECK: fcmovu %st(1), %st(0)
fcmovnb %st(1), %st(0) // CHECK: fcmovnb %st(1), %st(0)
fcmovne %st(1), %st(0) // CHECK: fcmovne %st(1), %st(0)
fcmovnbe %st(1), %st(0) // CHECK: fcmovnbe %st(1), %st(0)
fcmovnu %st(1), %st(0) // CHECK: fcmovnu %st(1), %st(0)
fcmovnae %st(1), %st(0) // CHECK: fcmovb %st(1), %st(0)
fcmovna %st(1), %st(0) // CHECK: fcmovbe %st(1), %st(0)
fcmovae %st(1), %st(0) // CHECK: fcmovnb %st(1), %st(0)
fcmova %st(1), %st(0) // CHECK: fcmovnbe %st(1), %st(0)
fix rdar://8456417 - llvm-mc can't do basic math git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114532 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:05:16 +00:00
// rdar://8456417
.byte 88 + 1 & 15 // CHECK: .byte 9
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8" Teaching the code generator about CR8-15, how to rex them up, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:29:50 +00:00
// rdar://8456412
mov %rdx, %cr0
// CHECK: movq %rdx, %cr0
// CHECK: encoding: [0x0f,0x22,0xc2]
mov %rdx, %cr4
// CHECK: movq %rdx, %cr4
// CHECK: encoding: [0x0f,0x22,0xe2]
mov %rdx, %cr8
// CHECK: movq %rdx, %cr8
// CHECK: encoding: [0x44,0x0f,0x22,0xc2]
mov %rdx, %cr15
// CHECK: movq %rdx, %cr15
// CHECK: encoding: [0x44,0x0f,0x22,0xfa]
fix rdar://8456371 - Handle commutable instructions written backward. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 06:26:39 +00:00
// rdar://8456371 - Handle commutable instructions written backward.
// CHECK: faddp %st(1)
// CHECK: fmulp %st(2)
faddp %st, %st(1)
fmulp %st, %st(2)
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands. My previous fix for rdar://8456371 should only apply to fmulp/faddp, not to fmul/fadd. Instruction set orthogonality is overrated or something. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:08:21 +00:00
// rdar://8468087 - Encode these accurately, they are not synonyms.
// CHECK: fmul %st(0), %st(1)
// CHECK: encoding: [0xdc,0xc9]
// CHECK: fmul %st(1)
// CHECK: encoding: [0xd8,0xc9]
fmul %st, %st(1)
fmul %st(1), %st
// CHECK: fadd %st(0), %st(1)
// CHECK: encoding: [0xdc,0xc1]
// CHECK: fadd %st(1)
// CHECK: encoding: [0xd8,0xc1]
fadd %st, %st(1)
fadd %st(1), %st
implement support for 'clr' alias. This is part of rdar://8416805, but balrog was wanting it on irc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 04:23:03 +00:00
// rdar://8416805
// CHECK: xorb %al, %al
// CHECK: encoding: [0x30,0xc0]
// CHECK: xorw %di, %di
// CHECK: encoding: [0x66,0x31,0xff]
// CHECK: xorl %esi, %esi
// CHECK: encoding: [0x31,0xf6]
// CHECK: xorq %rsi, %rsi
// CHECK: encoding: [0x48,0x31,0xf6]
clrb %al
clr %di
clr %esi
clr %rsi
add a couple more aliases, rdar://8456378 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114821 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:21:41 +00:00
// rdar://8456378
cltq // CHECK: cltq
cdqe // CHECK: cltq
cwde // CHECK: cwtl
cwtl // CHECK: cwtl
fix rdar://8456371 - Handle commutable instructions written backward. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 06:26:39 +00:00
yet more aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 07:24:57 +00:00
// rdar://8416805
cbw // CHECK: cbtw
cwd // CHECK: cwtd
cdq // CHECK: cltd
implement rdar://8456378 and PR7557 - support for the fstsw, an instruction that requires a WHOLE NEW wonderful kind of alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 01:50:45 +00:00
// rdar://8456378 and PR7557 - fstsw
fstsw %ax
// CHECK: wait
// CHECK: fnstsw %ax
fstsw (%rax)
// CHECK: wait
// CHECK: fnstsw (%rax)
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:24:57 +00:00
// rdar://8456382 - cvtsd2si support.
cvtsd2si %xmm1, %rax
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 04:55:40 +00:00
// CHECK: cvtsd2siq %xmm1, %rax
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:24:57 +00:00
// CHECK: encoding: [0xf2,0x48,0x0f,0x2d,0xc1]
cvtsd2si %xmm1, %eax
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 04:55:40 +00:00
// CHECK: cvtsd2sil %xmm1, %eax
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:24:57 +00:00
// CHECK: encoding: [0xf2,0x0f,0x2d,0xc1]
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115027 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 04:55:40 +00:00
cvtsd2siq %xmm0, %rax // CHECK: cvtsd2siq %xmm0, %rax
cvtsd2sil %xmm0, %eax // CHECK: cvtsd2sil %xmm0, %eax
cvtsd2si %xmm0, %rax // CHECK: cvtsd2siq %xmm0, %rax
add asmparser support for cvttpd2dq by removing some Int_ prefixes. Clean up cvttps2dq by removing some redundant implementations of the same instruction. rdar://8456382 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:36:32 +00:00
cvttpd2dq %xmm1, %xmm0 // CHECK: cvttpd2dq %xmm1, %xmm0
cvttpd2dq (%rax), %xmm0 // CHECK: cvttpd2dq (%rax), %xmm0
cvttps2dq %xmm1, %xmm0 // CHECK: cvttps2dq %xmm1, %xmm0
cvttps2dq (%rax), %xmm0 // CHECK: cvttps2dq (%rax), %xmm0
add basic avx support to the disassembler, also teach it about ssmem/sdmem operands. With this done, we can remove the _Int suffixes from the round instructions without the disassembler blowing up. This allows the assembler to support them, implementing rdar://8456376 - llvm-mc rejects 'roundss' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 02:57:56 +00:00
// rdar://8456376 - llvm-mc rejects 'roundss'
roundss $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x0a,0xc0,0x0e]
roundps $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x08,0xc0,0x0e]
roundsd $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x0b,0xc0,0x0e]
roundpd $0xE, %xmm0, %xmm0 // CHECK: encoding: [0x66,0x0f,0x3a,0x09,0xc0,0x0e]
implement support for 32-bit address operands in 64-bit mode, which are defined to emit the 0x67 prefix byte. rdar://8482675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 03:33:25 +00:00
// rdar://8482675 - 32-bit mem operand support in 64-bit mode (0x67 prefix)
leal 8(%eax), %esi
// CHECK: leal 8(%eax), %esi
// CHECK: encoding: [0x67,0x8d,0x70,0x08]
leaq 8(%eax), %rsi
// CHECK: leaq 8(%eax), %rsi
// CHECK: encoding: [0x67,0x48,0x8d,0x70,0x08]
leaq 8(%rax), %rsi
// CHECK: leaq 8(%rax), %rsi
// CHECK: encoding: [0x48,0x8d,0x70,0x08]
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same order as cctools for diffability. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 03:43:43 +00:00
cvttpd2dq 0xdeadbeef(%ebx,%ecx,8),%xmm5
// CHECK: cvttpd2dq 3735928559(%ebx,%ecx,8), %xmm5
// CHECK: encoding: [0x67,0x66,0x0f,0xe6,0xac,0xcb,0xef,0xbe,0xad,0xde]
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 05:05:03 +00:00
// rdar://8490728 - llvm-mc rejects 'movmskpd'
movmskpd %xmm6, %rax
// CHECK: movmskpd %xmm6, %rax
// CHECK: encoding: [0x66,0x48,0x0f,0x50,0xc6]
movmskpd %xmm6, %eax
// CHECK: movmskpd %xmm6, %eax
// CHECK: encoding: [0x66,0x0f,0x50,0xc6]
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