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llvm-6502/test/MC/Mips/mips5/valid-xfail.s

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[mips] Added a full set of instruction test cases for all ISA's (but not ASE's). Summary: Where those ISA's are not currently supported, the test is run with the smallest superset of that ISA. Some instructions are valid but don't pass yet. These have been placed in the valid-xfail.s's which will XPASS if _any_ instruction starts working. The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3214 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205180 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 12:13:12 +00:00
# Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding.
#
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208327 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 15:17:29 +00:00
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | not FileCheck %s
[mips] Added a full set of instruction test cases for all ISA's (but not ASE's). Summary: Where those ISA's are not currently supported, the test is run with the smallest superset of that ISA. Some instructions are valid but don't pass yet. These have been placed in the valid-xfail.s's which will XPASS if _any_ instruction starts working. The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3214 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205180 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 12:13:12 +00:00
# CHECK-NOT: encoding
# XFAIL: *
.set noat
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208327 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 15:17:29 +00:00
abs.ps $f22,$f8
add.ps $f25,$f27,$f13
alnv.ps $f12,$f18,$f30,$12
c.eq.ps $fcc5,$f0,$f9
c.f.ps $fcc6,$f11,$f11
c.le.ps $fcc1,$f7,$f20
c.lt.ps $f19,$f5
c.nge.ps $f1,$f26
c.ngl.ps $f21,$f30
c.ngle.ps $fcc7,$f12,$f20
c.ngt.ps $fcc5,$f30,$f6
c.ole.ps $fcc7,$f21,$f8
c.olt.ps $fcc3,$f7,$f16
c.seq.ps $fcc6,$f31,$f14
c.sf.ps $fcc6,$f4,$f6
c.ueq.ps $fcc1,$f5,$f29
c.ule.ps $fcc6,$f17,$f3
c.ult.ps $fcc7,$f14,$f0
c.un.ps $fcc4,$f2,$f26
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
madd.d $f18,$f19,$f26,$f20
madd.ps $f22,$f3,$f14,$f3
madd.s $f1,$f31,$f19,$f25
mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2
movz.ps $f18,$f17,$ra
msub.d $f10,$f1,$f31,$f18
msub.ps $f12,$f14,$f29,$f17
msub.s $f12,$f19,$f10,$f16
mul.ps $f14,$f0,$f16
neg.ps $f19,$f13
nmadd.d $f18,$f9,$f14,$f19
nmadd.ps $f27,$f4,$f9,$f25
nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30
nmsub.ps $f6,$f12,$f14,$f17
nmsub.s $f1,$f24,$f19,$f4
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
pul.ps $f9,$f30,$f26
puu.ps $f24,$f9,$f2
recip.d $f19,$f6
recip.s $f3,$f30
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sub.ps $f5,$f14,$f26
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