2003-12-18 13:06:04 +00:00
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//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2003-12-18 13:06:04 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2004-01-04 23:09:24 +00:00
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// This file implements the TwoAddress instruction pass which is used
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// by most register allocators. Two-Address instructions are rewritten
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// from:
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//
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// A = B op C
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//
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// to:
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//
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// A = B
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2004-02-04 22:17:40 +00:00
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// A op= C
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2003-12-18 13:06:04 +00:00
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//
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2004-02-04 22:17:40 +00:00
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// Note that if a register allocator chooses to use this pass, that it
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// has to be capable of handling the non-SSA nature of these rewritten
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// virtual registers.
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//
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// It is also worth noting that the duplicate operand of the two
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// address instruction is removed.
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2004-01-31 21:07:15 +00:00
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//
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2003-12-18 13:06:04 +00:00
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "twoaddrinstr"
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2004-01-31 21:07:15 +00:00
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#include "llvm/CodeGen/Passes.h"
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2004-07-21 23:17:57 +00:00
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#include "llvm/Function.h"
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2003-12-18 13:06:04 +00:00
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-02-10 18:45:23 +00:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2003-12-18 13:06:04 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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2008-05-26 05:49:49 +00:00
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#include "llvm/Support/CommandLine.h"
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2006-08-27 12:54:02 +00:00
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#include "llvm/Support/Compiler.h"
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2008-03-13 06:37:55 +00:00
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#include "llvm/Support/Debug.h"
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A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
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#include "llvm/ADT/SmallPtrSet.h"
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2004-09-01 22:55:40 +00:00
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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2003-12-18 13:06:04 +00:00
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using namespace llvm;
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2006-12-19 22:41:21 +00:00
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STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
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STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
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STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
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2008-03-13 06:37:55 +00:00
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STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
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2008-05-26 05:49:49 +00:00
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static cl::opt<bool>
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EnableReMat("2-addr-remat", cl::init(false), cl::Hidden,
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cl::desc("Two-addr conversion should remat when possible."));
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2006-12-19 22:41:21 +00:00
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namespace {
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2008-05-10 00:12:52 +00:00
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class VISIBILITY_HIDDEN TwoAddressInstructionPass
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: public MachineFunctionPass {
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2008-03-13 06:37:55 +00:00
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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LiveVariables *LV;
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2008-05-10 00:12:52 +00:00
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bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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2008-03-13 06:37:55 +00:00
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public:
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2007-05-06 13:37:16 +00:00
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static char ID; // Pass identification, replacement for typeid
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2007-05-01 21:15:47 +00:00
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TwoAddressInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
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2008-05-10 00:12:52 +00:00
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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AU.addPreservedID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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2003-12-18 22:40:24 +00:00
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2008-05-10 00:12:52 +00:00
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/// runOnMachineFunction - Pass entry point.
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2004-07-22 15:26:23 +00:00
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bool runOnMachineFunction(MachineFunction&);
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};
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2006-05-24 17:04:05 +00:00
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}
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2003-12-18 13:06:04 +00:00
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2008-05-13 00:00:25 +00:00
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char TwoAddressInstructionPass::ID = 0;
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static RegisterPass<TwoAddressInstructionPass>
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X("twoaddressinstruction", "Two-Address instruction pass");
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2008-05-13 02:05:11 +00:00
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const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
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2003-12-18 22:40:24 +00:00
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2008-03-13 06:37:55 +00:00
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/// Sink3AddrInstruction - A two-address instruction has been converted to a
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/// three-address instruction to avoid clobbering a register. Try to sink it
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2008-05-10 00:12:52 +00:00
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/// past the instruction that would kill the above mentioned register to reduce
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/// register pressure.
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///
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2008-03-13 06:37:55 +00:00
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bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
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MachineInstr *MI, unsigned SavedReg,
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MachineBasicBlock::iterator OldPos) {
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// Check if it's safe to move this instruction.
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bool SeenStore = true; // Be conservative.
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if (!MI->isSafeToMove(TII, SeenStore))
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return false;
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unsigned DefReg = 0;
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SmallSet<unsigned, 4> UseRegs;
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2008-05-10 00:12:52 +00:00
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2008-03-13 06:37:55 +00:00
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isRegister())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (MO.isUse() && MOReg != SavedReg)
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UseRegs.insert(MO.getReg());
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if (!MO.isDef())
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continue;
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if (MO.isImplicit())
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// Don't try to move it if it implicitly defines a register.
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return false;
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if (DefReg)
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// For now, don't move any instructions that define multiple registers.
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return false;
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DefReg = MO.getReg();
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}
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// Find the instruction that kills SavedReg.
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MachineInstr *KillMI = NULL;
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2008-05-10 00:12:52 +00:00
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2008-03-13 06:37:55 +00:00
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
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UE = MRI->use_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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if (!UseMO.isKill())
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continue;
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KillMI = UseMO.getParent();
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break;
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}
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2008-05-10 00:12:52 +00:00
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2008-03-13 06:37:55 +00:00
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if (!KillMI || KillMI->getParent() != MBB)
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return false;
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2008-05-10 00:12:52 +00:00
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// If any of the definitions are used by another instruction between the
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// position and the kill use, then it's not safe to sink it.
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//
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// FIXME: This can be sped up if there is an easy way to query whether an
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// instruction if before or after another instruction. Then we can use
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// MachineRegisterInfo def / use instead.
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2008-03-13 06:37:55 +00:00
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MachineOperand *KillMO = NULL;
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MachineBasicBlock::iterator KillPos = KillMI;
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++KillPos;
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2008-05-10 00:12:52 +00:00
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2008-03-13 06:37:55 +00:00
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for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) {
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MachineInstr *OtherMI = I;
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2008-05-10 00:12:52 +00:00
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2008-03-13 06:37:55 +00:00
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for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = OtherMI->getOperand(i);
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if (!MO.isRegister())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (DefReg == MOReg)
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return false;
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2008-05-10 00:12:52 +00:00
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2008-03-13 06:37:55 +00:00
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if (MO.isKill()) {
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if (OtherMI == KillMI && MOReg == SavedReg)
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// Save the operand that kills the register. We want unset the kill
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// marker is we can sink MI past it.
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KillMO = &MO;
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else if (UseRegs.count(MOReg))
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// One of the uses is killed before the destination.
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return false;
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}
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}
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}
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// Update kill and LV information.
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KillMO->setIsKill(false);
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KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
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KillMO->setIsKill(true);
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LiveVariables::VarInfo& VarInfo = LV->getVarInfo(SavedReg);
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VarInfo.removeKill(KillMI);
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VarInfo.Kills.push_back(MI);
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// Move instruction to its destination.
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MBB->remove(MI);
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MBB->insert(KillPos, MI);
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++Num3AddrSunk;
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return true;
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}
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2008-05-10 00:12:52 +00:00
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/// runOnMachineFunction - Reduce two-address instructions to two operands.
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2003-12-18 13:06:04 +00:00
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///
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2004-01-31 21:14:04 +00:00
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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2006-11-28 22:48:48 +00:00
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DOUT << "Machine Function\n";
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2004-07-22 15:26:23 +00:00
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const TargetMachine &TM = MF.getTarget();
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2008-03-13 06:37:55 +00:00
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MRI = &MF.getRegInfo();
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TII = TM.getInstrInfo();
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TRI = TM.getRegisterInfo();
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LV = &getAnalysis<LiveVariables>();
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2004-07-22 15:26:23 +00:00
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bool MadeChange = false;
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2006-11-28 22:48:48 +00:00
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DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n";
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DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
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2004-07-22 15:26:23 +00:00
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A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
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SmallPtrSet<MachineInstr*, 8> ReMattedInstrs;
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2004-07-22 15:26:23 +00:00
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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2008-03-27 01:27:25 +00:00
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mi != me; ) {
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MachineBasicBlock::iterator nmi = next(mi);
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2008-01-07 07:27:27 +00:00
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const TargetInstrDesc &TID = mi->getDesc();
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2006-11-01 23:06:55 +00:00
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bool FirstTied = true;
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2008-05-10 00:12:52 +00:00
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2008-01-07 07:27:27 +00:00
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for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
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int ti = TID.getOperandConstraint(si, TOI::TIED_TO);
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2006-11-01 23:06:55 +00:00
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if (ti == -1)
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continue;
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if (FirstTied) {
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++NumTwoAddressInstrs;
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2006-12-07 20:28:15 +00:00
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DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM));
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2006-11-01 23:06:55 +00:00
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}
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2008-05-10 00:12:52 +00:00
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2006-11-01 23:06:55 +00:00
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FirstTied = false;
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assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() &&
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mi->getOperand(si).isUse() && "two address instruction invalid");
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2008-05-10 00:12:52 +00:00
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// If the two operands are the same we just remove the use
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2006-11-01 23:06:55 +00:00
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// and mark the def as def&use, otherwise we have to insert a copy.
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if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
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2008-05-10 00:12:52 +00:00
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// Rewrite:
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2006-11-01 23:06:55 +00:00
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(ti).getReg();
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unsigned regB = mi->getOperand(si).getReg();
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2008-02-10 18:45:23 +00:00
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assert(TargetRegisterInfo::isVirtualRegister(regA) &&
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TargetRegisterInfo::isVirtualRegister(regB) &&
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2006-11-01 23:06:55 +00:00
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"cannot update physical register live information");
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2004-07-22 15:26:23 +00:00
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2004-07-21 23:17:57 +00:00
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#ifndef NDEBUG
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2006-11-01 23:06:55 +00:00
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// First, verify that we don't have a use of a in the instruction (a =
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// b + a for example) because our transformation will not work. This
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// should never occur because we are in SSA form.
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for (unsigned i = 0; i != mi->getNumOperands(); ++i)
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assert((int)i == ti ||
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!mi->getOperand(i).isRegister() ||
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mi->getOperand(i).getReg() != regA);
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2004-07-21 23:17:57 +00:00
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#endif
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2004-02-04 22:17:40 +00:00
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2006-11-01 23:06:55 +00:00
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// If this instruction is not the killing user of B, see if we can
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// rearrange the code to make it so. Making it the killing user will
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// allow us to coalesce A and B together, eliminating the copy we are
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// about to insert.
|
2008-03-05 00:59:57 +00:00
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if (!mi->killsRegister(regB)) {
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2006-11-01 23:06:55 +00:00
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// If this instruction is commutative, check to see if C dies. If
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// so, swap the B and C operands. This makes the live ranges of A
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// and C joinable.
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// FIXME: This code also works for A := B op C instructions.
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2008-01-07 07:27:27 +00:00
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if (TID.isCommutable() && mi->getNumOperands() >= 3) {
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2006-11-01 23:06:55 +00:00
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assert(mi->getOperand(3-si).isRegister() &&
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"Not a proper commutative instruction!");
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unsigned regC = mi->getOperand(3-si).getReg();
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2008-05-10 00:12:52 +00:00
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|
|
2008-03-05 00:59:57 +00:00
|
|
|
if (mi->killsRegister(regC)) {
|
2006-11-28 22:48:48 +00:00
|
|
|
DOUT << "2addr: COMMUTING : " << *mi;
|
2008-03-13 06:37:55 +00:00
|
|
|
MachineInstr *NewMI = TII->commuteInstruction(mi);
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2006-11-01 23:06:55 +00:00
|
|
|
if (NewMI == 0) {
|
2006-11-28 22:48:48 +00:00
|
|
|
DOUT << "2addr: COMMUTING FAILED!\n";
|
2006-11-01 23:06:55 +00:00
|
|
|
} else {
|
2006-11-28 22:48:48 +00:00
|
|
|
DOUT << "2addr: COMMUTED TO: " << *NewMI;
|
2006-11-01 23:06:55 +00:00
|
|
|
// If the instruction changed to commute it, update livevar.
|
|
|
|
if (NewMI != mi) {
|
2008-03-13 06:37:55 +00:00
|
|
|
LV->instructionChanged(mi, NewMI); // Update live variables
|
2006-11-01 23:06:55 +00:00
|
|
|
mbbi->insert(mi, NewMI); // Insert the new inst
|
|
|
|
mbbi->erase(mi); // Nuke the old inst.
|
|
|
|
mi = NewMI;
|
|
|
|
}
|
|
|
|
|
|
|
|
++NumCommuted;
|
|
|
|
regB = regC;
|
|
|
|
goto InstructionRearranged;
|
2005-04-21 22:36:52 +00:00
|
|
|
}
|
2005-01-19 07:08:42 +00:00
|
|
|
}
|
Make the 2-address instruction lowering pass smarter in two ways:
1. If we are two-addressing a commutable instruction and the LHS is not the
last use of the variable, see if the instruction is the last use of the
RHS. If so, commute the instruction, allowing us to avoid a
register-register copy in many cases for common instructions like ADD, OR,
AND, etc on X86.
2. If #1 doesn't hold, and if this is an instruction that also existing in
3-address form, promote the instruction to a 3-address instruction to
avoid the register-register copy. We can do this for several common
instructions in X86, including ADDrr, INC, DEC, etc.
This patch implements test/Regression/CodeGen/X86/commute-two-addr.ll,
overlap-add.ll, and overlap-shift.ll when I check in the X86 support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19245 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-02 02:34:12 +00:00
|
|
|
}
|
2006-11-01 23:06:55 +00:00
|
|
|
|
|
|
|
// If this instruction is potentially convertible to a true
|
|
|
|
// three-address instruction,
|
2008-01-07 07:27:27 +00:00
|
|
|
if (TID.isConvertibleTo3Addr()) {
|
2006-11-01 23:06:55 +00:00
|
|
|
// FIXME: This assumes there are no more operands which are tied
|
|
|
|
// to another register.
|
|
|
|
#ifndef NDEBUG
|
2008-05-10 00:12:52 +00:00
|
|
|
for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i)
|
2008-01-07 07:27:27 +00:00
|
|
|
assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
|
2006-11-01 23:06:55 +00:00
|
|
|
#endif
|
|
|
|
|
2008-03-13 06:37:55 +00:00
|
|
|
if (MachineInstr *New=TII->convertToThreeAddress(mbbi, mi, *LV)) {
|
2006-11-28 22:48:48 +00:00
|
|
|
DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
|
|
|
|
DOUT << "2addr: TO 3-ADDR: " << *New;
|
2008-03-13 07:56:58 +00:00
|
|
|
bool Sunk = false;
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2008-03-13 08:04:35 +00:00
|
|
|
if (New->findRegisterUseOperand(regB, false, TRI))
|
2008-03-13 07:56:58 +00:00
|
|
|
// FIXME: Temporary workaround. If the new instruction doesn't
|
|
|
|
// uses regB, convertToThreeAddress must have created more
|
|
|
|
// then one instruction.
|
|
|
|
Sunk = Sink3AddrInstruction(mbbi, New, regB, mi);
|
2008-05-10 00:12:52 +00:00
|
|
|
|
|
|
|
mbbi->erase(mi); // Nuke the old inst.
|
|
|
|
|
2008-03-27 01:27:25 +00:00
|
|
|
if (!Sunk) {
|
|
|
|
mi = New;
|
|
|
|
nmi = next(mi);
|
|
|
|
}
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2006-11-01 23:06:55 +00:00
|
|
|
++NumConvertedTo3Addr;
|
2008-05-10 00:12:52 +00:00
|
|
|
break; // Done with this instruction.
|
2006-11-01 23:06:55 +00:00
|
|
|
}
|
2007-10-20 04:01:47 +00:00
|
|
|
}
|
Make the 2-address instruction lowering pass smarter in two ways:
1. If we are two-addressing a commutable instruction and the LHS is not the
last use of the variable, see if the instruction is the last use of the
RHS. If so, commute the instruction, allowing us to avoid a
register-register copy in many cases for common instructions like ADD, OR,
AND, etc on X86.
2. If #1 doesn't hold, and if this is an instruction that also existing in
3-address form, promote the instruction to a 3-address instruction to
avoid the register-register copy. We can do this for several common
instructions in X86, including ADDrr, INC, DEC, etc.
This patch implements test/Regression/CodeGen/X86/commute-two-addr.ll,
overlap-add.ll, and overlap-shift.ll when I check in the X86 support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19245 91177308-0d34-0410-b5e6-96231b3b80d8
2005-01-02 02:34:12 +00:00
|
|
|
}
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2006-11-01 23:06:55 +00:00
|
|
|
InstructionRearranged:
|
2007-12-31 04:13:23 +00:00
|
|
|
const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA);
|
A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
|
|
|
MachineInstr *Orig = MRI->getVRegDef(regB);
|
2008-05-29 01:02:09 +00:00
|
|
|
const TargetInstrDesc &OrigTID = Orig->getDesc();
|
2008-05-28 22:52:47 +00:00
|
|
|
bool SawStore = false;
|
A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
|
|
|
|
2008-05-28 22:52:47 +00:00
|
|
|
if (EnableReMat && Orig && Orig->isSafeToMove(TII, SawStore) &&
|
2008-05-29 01:02:09 +00:00
|
|
|
OrigTID.isAsCheapAsAMove() && !OrigTID.mayLoad() &&
|
|
|
|
!OrigTID.isSimpleLoad()) {
|
|
|
|
DEBUG(cerr << "2addr: REMATTING : " << *Orig << "\n");
|
A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
|
|
|
TII->reMaterialize(*mbbi, mi, regA, Orig);
|
|
|
|
ReMattedInstrs.insert(Orig);
|
|
|
|
} else {
|
|
|
|
TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
|
|
|
|
}
|
2006-11-01 23:06:55 +00:00
|
|
|
|
|
|
|
MachineBasicBlock::iterator prevMi = prior(mi);
|
2006-12-07 20:28:15 +00:00
|
|
|
DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2008-05-10 00:12:52 +00:00
|
|
|
// Update live variables for regB.
|
2008-03-13 06:37:55 +00:00
|
|
|
LiveVariables::VarInfo& varInfoB = LV->getVarInfo(regB);
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2007-11-08 01:20:48 +00:00
|
|
|
// regB is used in this BB.
|
|
|
|
varInfoB.UsedBlocks[mbbi->getNumber()] = true;
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2008-03-13 06:37:55 +00:00
|
|
|
if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
|
|
|
|
LV->addVirtualRegisterKilled(regB, prevMi);
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2008-03-13 06:37:55 +00:00
|
|
|
if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
|
|
|
|
LV->addVirtualRegisterDead(regB, prevMi);
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2008-05-10 00:12:52 +00:00
|
|
|
// Replace all occurences of regB with regA.
|
2006-11-01 23:06:55 +00:00
|
|
|
for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
|
|
|
|
if (mi->getOperand(i).isRegister() &&
|
|
|
|
mi->getOperand(i).getReg() == regB)
|
|
|
|
mi->getOperand(i).setReg(regA);
|
|
|
|
}
|
2004-07-22 15:26:23 +00:00
|
|
|
}
|
|
|
|
|
2006-11-01 23:06:55 +00:00
|
|
|
assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
|
|
|
|
mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
|
|
|
|
MadeChange = true;
|
2004-07-22 15:26:23 +00:00
|
|
|
|
2006-12-07 20:28:15 +00:00
|
|
|
DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM));
|
2006-11-01 23:06:55 +00:00
|
|
|
}
|
2008-05-10 00:12:52 +00:00
|
|
|
|
2008-03-27 01:27:25 +00:00
|
|
|
mi = nmi;
|
2003-12-18 13:06:04 +00:00
|
|
|
}
|
2004-07-22 15:26:23 +00:00
|
|
|
}
|
2003-12-18 13:06:04 +00:00
|
|
|
|
2008-05-26 05:49:49 +00:00
|
|
|
if (EnableReMat) {
|
2008-05-27 20:40:52 +00:00
|
|
|
// Check to see if the instructions that we rematerialized are now dead. If
|
|
|
|
// they are, expunge them here.
|
2008-05-26 05:49:49 +00:00
|
|
|
SmallPtrSet<MachineInstr*, 8>::iterator I = ReMattedInstrs.begin();
|
|
|
|
SmallPtrSet<MachineInstr*, 8>::iterator E = ReMattedInstrs.end();
|
|
|
|
|
|
|
|
for (; I != E; ++I) {
|
|
|
|
MachineInstr *MI = *I;
|
|
|
|
bool InstrDead = true;
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isRegister())
|
|
|
|
continue;
|
|
|
|
unsigned MOReg = MO.getReg();
|
2008-05-27 20:40:52 +00:00
|
|
|
|
|
|
|
if (!MOReg || !MO.isDef() || (MO.isImplicit() && MO.isDead()))
|
A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
|
|
|
continue;
|
|
|
|
|
2008-05-27 20:40:52 +00:00
|
|
|
if (MRI->use_begin(MOReg) != MRI->use_end()) {
|
|
|
|
InstrDead = false;
|
|
|
|
break;
|
A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-05-27 20:40:52 +00:00
|
|
|
if (InstrDead)
|
2008-05-26 05:49:49 +00:00
|
|
|
MI->eraseFromParent();
|
|
|
|
}
|
A problem that's exposed when machine LICM is enabled. Consider this code:
LBB1_3: # bb
...
xorl %ebp, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Whe using machine LICM, LLVM converts it into:
xorl %esi, %esi
LBB1_3: # bb
...
movl %esi, %ebp
subl (%ebx), %ebp
...
incl %ecx
cmpl %edi, %ecx
jl LBB1_3 # bb
Two address conversion inserts the copy instruction. However, it's cheaper to
rematerialize it, and remat helps reduce register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-26 05:18:34 +00:00
|
|
|
}
|
|
|
|
|
2004-07-22 15:26:23 +00:00
|
|
|
return MadeChange;
|
2003-12-18 13:06:04 +00:00
|
|
|
}
|