2008-01-01 01:12:31 +00:00
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//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
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2007-12-31 04:13:23 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implementation of the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2010-04-26 19:16:00 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2010-04-14 16:51:49 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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2011-08-09 16:46:27 +00:00
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#include "llvm/Target/TargetMachine.h"
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2007-12-31 04:13:23 +00:00
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using namespace llvm;
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2011-07-29 22:51:22 +00:00
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MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
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2012-03-27 15:13:58 +00:00
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: TRI(&TRI), IsSSA(true), TracksLiveness(true) {
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2007-12-31 04:13:23 +00:00
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VRegInfo.reserve(256);
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2009-06-14 20:22:55 +00:00
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RegAllocHints.reserve(256);
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2008-02-10 18:45:23 +00:00
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UsedPhysRegs.resize(TRI.getNumRegs());
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2012-02-17 19:07:56 +00:00
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UsedPhysRegMask.resize(TRI.getNumRegs());
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2008-01-01 01:12:31 +00:00
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// Create the physreg use/def lists.
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2008-02-10 18:45:23 +00:00
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PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
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memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
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2008-01-01 01:12:31 +00:00
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}
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MachineRegisterInfo::~MachineRegisterInfo() {
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#ifndef NDEBUG
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2012-02-21 04:51:23 +00:00
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clearVirtRegs();
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2008-07-07 19:55:35 +00:00
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for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
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assert(!PhysRegUseDefLists[i] &&
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"PhysRegUseDefLists has entries after all instructions are deleted");
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2008-01-01 01:12:31 +00:00
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#endif
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delete [] PhysRegUseDefLists;
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}
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2009-04-15 01:19:35 +00:00
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/// setRegClass - Set the register class of the specified virtual register.
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///
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void
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MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
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VRegInfo[Reg].first = RC;
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}
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2010-10-06 23:54:39 +00:00
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const TargetRegisterClass *
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MachineRegisterInfo::constrainRegClass(unsigned Reg,
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2011-09-22 21:39:31 +00:00
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const TargetRegisterClass *RC,
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unsigned MinNumRegs) {
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2010-10-06 23:54:39 +00:00
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const TargetRegisterClass *OldRC = getRegClass(Reg);
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if (OldRC == RC)
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return RC;
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2011-09-30 22:18:51 +00:00
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const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
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2011-09-22 21:39:31 +00:00
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if (!NewRC || NewRC == OldRC)
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return NewRC;
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if (NewRC->getNumRegs() < MinNumRegs)
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2010-10-06 23:54:39 +00:00
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return 0;
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2011-09-22 21:39:31 +00:00
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setRegClass(Reg, NewRC);
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2010-10-06 23:54:39 +00:00
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return NewRC;
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}
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2011-08-09 16:46:27 +00:00
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bool
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MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
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const TargetInstrInfo *TII = TM.getInstrInfo();
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const TargetRegisterClass *OldRC = getRegClass(Reg);
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const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
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// Stop early if there is no room to grow.
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if (NewRC == OldRC)
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return false;
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// Accumulate constraints from all uses.
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for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
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++I) {
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const TargetRegisterClass *OpRC =
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2011-10-12 23:37:40 +00:00
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I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
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2011-12-19 16:53:37 +00:00
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if (unsigned SubIdx = I.getOperand().getSubReg()) {
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if (OpRC)
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NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
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else
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NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
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} else if (OpRC)
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2011-09-30 22:18:51 +00:00
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NewRC = TRI->getCommonSubClass(NewRC, OpRC);
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2011-08-09 16:46:27 +00:00
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if (!NewRC || NewRC == OldRC)
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return false;
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}
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setRegClass(Reg, NewRC);
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return true;
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}
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2008-12-08 04:54:11 +00:00
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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///
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unsigned
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MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
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assert(RegClass && "Cannot create register without RegClass!");
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2011-06-02 23:07:20 +00:00
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assert(RegClass->isAllocatable() &&
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"Virtual register RegClass must be allocatable.");
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2011-01-09 03:05:46 +00:00
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// New virtual register number.
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unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
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2008-12-08 04:54:11 +00:00
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// Add a reg, but keep track of whether the vector reallocated or not.
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2011-01-09 03:05:46 +00:00
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const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
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void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
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VRegInfo.grow(Reg);
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VRegInfo[Reg].first = RegClass;
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RegAllocHints.grow(Reg);
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2008-12-08 04:54:11 +00:00
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2011-01-09 03:05:46 +00:00
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if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
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2008-12-08 04:54:11 +00:00
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// The vector reallocated, handle this now.
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HandleVRegListReallocation();
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2011-01-09 03:05:46 +00:00
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return Reg;
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2008-12-08 04:54:11 +00:00
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}
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2012-02-21 04:51:23 +00:00
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/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
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void MachineRegisterInfo::clearVirtRegs() {
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#ifndef NDEBUG
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for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
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assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
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"Vreg use list non-empty still?");
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#endif
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VRegInfo.clear();
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}
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2008-01-01 01:12:31 +00:00
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/// HandleVRegListReallocation - We just added a virtual register to the
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/// VRegInfo info list and it reallocated. Update the use/def lists info
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/// pointers.
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void MachineRegisterInfo::HandleVRegListReallocation() {
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// The back pointers for the vreg lists point into the previous vector.
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// Update them to point to their correct slots.
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2011-01-09 03:05:46 +00:00
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for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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MachineOperand *List = VRegInfo[Reg].second;
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2008-01-01 01:12:31 +00:00
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if (!List) continue;
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// Update the back-pointer to be accurate once more.
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2011-01-09 03:05:46 +00:00
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List->Contents.Reg.Prev = &VRegInfo[Reg].second;
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2008-01-01 01:12:31 +00:00
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}
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2007-12-31 04:13:23 +00:00
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}
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2008-01-01 03:07:29 +00:00
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2008-01-01 20:36:19 +00:00
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/// replaceRegWith - Replace all instances of FromReg with ToReg in the
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/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
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/// except that it also changes any definitions of the register as well.
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void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
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assert(FromReg != ToReg && "Cannot replace a reg with itself");
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// TODO: This could be more efficient by bulk changing the operands.
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for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
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MachineOperand &O = I.getOperand();
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++I;
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O.setReg(ToReg);
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}
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}
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2008-01-01 03:07:29 +00:00
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/// getVRegDef - Return the machine instr that defines the specified virtual
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/// register or null if none is found. This assumes that the code is in SSA
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/// form, so there should only be one definition.
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MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
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2009-09-25 22:26:13 +00:00
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// Since we are in SSA form, we can use the first definition.
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2012-03-10 12:50:44 +00:00
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def_iterator I = def_begin(Reg);
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return !I.atEnd() ? &*I : 0;
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2008-01-01 03:07:29 +00:00
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}
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2008-02-13 02:45:38 +00:00
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2010-03-03 21:18:38 +00:00
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bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
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use_iterator UI = use_begin(RegNo);
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if (UI == use_end())
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return false;
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return ++UI == use_end();
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}
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bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
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use_nodbg_iterator UI = use_nodbg_begin(RegNo);
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if (UI == use_nodbg_end())
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return false;
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return ++UI == use_nodbg_end();
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}
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2008-02-13 02:45:38 +00:00
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2010-05-13 19:24:00 +00:00
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/// clearKillFlags - Iterate over all the uses of the given register and
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/// clear the kill flag from the MachineOperand. This function is used by
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/// optimization passes which extend register lifetimes and need only
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/// preserve conservative kill flag information.
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void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
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for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
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UI.getOperand().setIsKill(false);
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}
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2010-04-13 16:55:37 +00:00
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bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->first == Reg || I->second == Reg)
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return true;
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return false;
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}
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bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
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for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
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if (*I == Reg)
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return true;
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return false;
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}
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2010-04-28 23:08:54 +00:00
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/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
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/// corresponding live-in physical register.
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unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->second == VReg)
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return I->first;
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return 0;
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}
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2010-05-24 21:33:37 +00:00
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/// getLiveInVirtReg - If PReg is a live-in physical register, return the
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/// corresponding live-in physical register.
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unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->first == PReg)
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return I->second;
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return 0;
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}
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2010-04-14 16:51:49 +00:00
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/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
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/// into the given entry block.
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void
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MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
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const TargetRegisterInfo &TRI,
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const TargetInstrInfo &TII) {
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2010-05-29 02:23:39 +00:00
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// Emit the copies into the top of the block.
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2010-06-24 22:23:02 +00:00
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for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
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if (LiveIns[i].second) {
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if (use_empty(LiveIns[i].second)) {
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// The livein has no uses. Drop it.
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//
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// It would be preferable to have isel avoid creating live-in
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// records for unused arguments in the first place, but it's
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// complicated by the debug info code for arguments.
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LiveIns.erase(LiveIns.begin() + i);
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--i; --e;
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} else {
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// Emit a copy.
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2011-02-21 23:21:26 +00:00
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BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
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2010-07-10 22:42:59 +00:00
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TII.get(TargetOpcode::COPY), LiveIns[i].second)
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.addReg(LiveIns[i].first);
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2010-06-24 22:23:02 +00:00
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// Add the register to the entry block live-in set.
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EntryMBB->addLiveIn(LiveIns[i].first);
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}
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} else {
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// Add the register to the entry block live-in set.
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EntryMBB->addLiveIn(LiveIns[i].first);
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2010-05-29 02:23:39 +00:00
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}
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2010-04-14 16:51:49 +00:00
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}
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2008-02-13 02:45:38 +00:00
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#ifndef NDEBUG
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void MachineRegisterInfo::dumpUses(unsigned Reg) const {
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for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
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I.getOperand().getParent()->dump();
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}
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#endif
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2012-01-05 00:26:49 +00:00
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void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
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ReservedRegs = TRI->getReservedRegs(MF);
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}
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2012-01-16 22:34:08 +00:00
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bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
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const MachineFunction &MF) const {
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assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
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// Check if any overlapping register is modified.
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2012-06-01 23:28:30 +00:00
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for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
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if (!def_empty(*AI))
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2012-01-16 22:34:08 +00:00
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return false;
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// Check if any overlapping register is allocatable so it may be used later.
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if (AllocatableRegs.empty())
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AllocatableRegs = TRI->getAllocatableSet(MF);
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2012-06-01 23:28:30 +00:00
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for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
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if (AllocatableRegs.test(*AI))
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2012-01-16 22:34:08 +00:00
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return false;
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return true;
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}
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