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Move getCommonSubClass() into TRI.

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It will soon need the context.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-09-30 22:18:51 +00:00
parent f9a4bb78da
commit e27e1ca3c9
8 changed files with 22 additions and 16 deletions
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2
include/llvm/CodeGen/LiveStackAnalysis.h
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@ -25,6 +25,8 @@
namespace llvm {
class LiveStacks : public MachineFunctionPass {
const TargetRegisterInfo *TRI;
/// Special pool allocator for VNInfo's (LiveInterval val#).
///
VNInfo::Allocator VNInfoAllocator;

2
include/llvm/CodeGen/MachineRegisterInfo.h
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@ -25,6 +25,8 @@ namespace llvm {
/// registers, including vreg register classes, use/def chains for registers,
/// etc.
class MachineRegisterInfo {
const TargetRegisterInfo *const TRI;
/// IsSSA - True when the machine function is in SSA form and virtual
/// registers have a single def.
bool IsSSA;

11
include/llvm/Target/TargetRegisterInfo.h
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@ -481,6 +481,12 @@ public:
return RegClassBegin[i];
}
/// getCommonSubClass - find the largest common subclass of A and B. Return
/// NULL if there is no common subclass.
const TargetRegisterClass *
getCommonSubClass(const TargetRegisterClass *A,
const TargetRegisterClass *B) const;
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
/// values. If a target supports multiple different pointer register classes,
/// kind specifies which one is indicated.
@ -701,11 +707,6 @@ struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
}
};
/// getCommonSubClass - find the largest common subclass of A and B. Return NULL
/// if there is no common subclass.
const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
const TargetRegisterClass *B);
/// PrintReg - Helper class for printing registers on a raw_ostream.
/// Prints virtual and physical registers with or without a TRI instance.
///

5
lib/CodeGen/LiveStackAnalysis.cpp
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@ -44,7 +44,8 @@ void LiveStacks::releaseMemory() {
S2RCMap.clear();
}
bool LiveStacks::runOnMachineFunction(MachineFunction &) {
bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
TRI = MF.getTarget().getRegisterInfo();
// FIXME: No analysis is being done right now. We are relying on the
// register allocators to provide the information.
return false;
@ -61,7 +62,7 @@ LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
} else {
// Use the largest common subclass register class.
const TargetRegisterClass *OldRC = S2RCMap[Slot];
S2RCMap[Slot] = getCommonSubClass(OldRC, RC);
S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
}
return I->second;
}

7
lib/CodeGen/MachineRegisterInfo.cpp
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@ -18,7 +18,7 @@
using namespace llvm;
MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
: IsSSA(true) {
: TRI(&TRI), IsSSA(true) {
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
UsedPhysRegs.resize(TRI.getNumRegs());
@ -54,7 +54,7 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg,
const TargetRegisterClass *OldRC = getRegClass(Reg);
if (OldRC == RC)
return RC;
const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
if (!NewRC || NewRC == OldRC)
return NewRC;
if (NewRC->getNumRegs() < MinNumRegs)
@ -66,7 +66,6 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg,
bool
MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
const TargetRegisterClass *OldRC = getRegClass(Reg);
const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
@ -86,7 +85,7 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
const TargetRegisterClass *OpRC =
TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
if (OpRC)
NewRC = getCommonSubClass(NewRC, OpRC);
NewRC = TRI->getCommonSubClass(NewRC, OpRC);
if (!NewRC || NewRC == OldRC)
return false;
}

4
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -289,7 +289,7 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
return false;
const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
if (!getCommonSubClass(DstRC, SrcRC))
if (!TRI.getCommonSubClass(DstRC, SrcRC))
return false;
SrcSub = DstSub = 0;
}
@ -309,7 +309,7 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
if (DstSub)
NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
else
NewRC = getCommonSubClass(DstRC, SrcRC);
NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
if (!NewRC)
return false;
CrossClass = NewRC != DstRC || NewRC != SrcRC;

3
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -113,7 +113,8 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
if (!UseRC)
UseRC = RC;
else if (RC) {
const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC);
const TargetRegisterClass *ComRC =
TRI->getCommonSubClass(UseRC, RC);
// If multiple uses expect disjoint register classes, we emit
// copies in AddRegisterOperand.
if (ComRC)

4
lib/Target/TargetRegisterInfo.cpp
View File

@ -98,8 +98,8 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
}
const TargetRegisterClass *
llvm::getCommonSubClass(const TargetRegisterClass *A,
const TargetRegisterClass *B) {
TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
const TargetRegisterClass *B) const {
// First take care of the trivial cases
if (A == B)
return A;