2005-08-17 19:33:03 +00:00
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//===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for 32 bit PowerPC,
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// converting from a legalized dag to a PPC dag.
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPC.h"
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#include "PPC32TargetMachine.h"
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#include "PPC32ISelLowering.h"
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2005-08-19 22:38:53 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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2005-08-17 19:33:03 +00:00
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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2005-08-19 22:38:53 +00:00
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#include "llvm/GlobalValue.h"
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2005-08-17 19:33:03 +00:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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namespace {
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Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
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Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
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//===--------------------------------------------------------------------===//
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/// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
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/// instructions for SelectionDAG operations.
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///
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class PPC32DAGToDAGISel : public SelectionDAGISel {
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PPC32TargetLowering PPC32Lowering;
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unsigned GlobalBaseReg;
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2005-08-17 19:33:03 +00:00
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public:
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PPC32DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
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2005-08-19 22:38:53 +00:00
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseReg = 0;
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return SelectionDAGISel::runOnFunction(Fn);
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}
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2005-08-17 19:33:03 +00:00
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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2005-08-19 22:38:53 +00:00
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/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
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/// base register. Return the virtual register that holds this value.
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SDOperand getGlobalBaseReg();
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2005-08-17 19:33:03 +00:00
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand Select(SDOperand Op);
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SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic = false,
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bool Negate = false);
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2005-08-19 00:38:14 +00:00
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SDNode *SelectBitfieldInsert(SDNode *N);
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2005-08-21 18:50:37 +00:00
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/// SelectCC - Select a comparison of the specified values with the
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/// specified condition code, returning the CR# of the expression.
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SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
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2005-08-21 22:31:09 +00:00
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/// SelectAddr - Given the specified address, return the two operands for a
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/// load/store instruction, and return true if it should be an indexed [r+r]
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/// operation.
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bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
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2005-08-17 19:33:03 +00:00
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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Select(DAG.getRoot());
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DAG.RemoveDeadNodes();
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2005-08-18 18:46:06 +00:00
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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2005-08-17 19:33:03 +00:00
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}
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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}
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};
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}
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2005-08-19 22:38:53 +00:00
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/// getGlobalBaseReg - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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2005-08-21 22:31:09 +00:00
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SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() {
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2005-08-19 22:38:53 +00:00
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if (!GlobalBaseReg) {
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = BB->getParent()->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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SSARegMap *RegMap = BB->getParent()->getSSARegMap();
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GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
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BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
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BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
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}
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2005-08-21 22:31:09 +00:00
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return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
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2005-08-19 22:38:53 +00:00
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}
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2005-08-18 05:00:13 +00:00
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isIntImmediate(SDNode *N, unsigned& Imm) {
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if (N->getOpcode() == ISD::Constant) {
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Imm = cast<ConstantSDNode>(N)->getValue();
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return true;
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}
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return false;
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}
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2005-08-18 07:30:46 +00:00
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// isOprShiftImm - Returns true if the specified operand is a shift opcode with
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// a immediate shift count less than 32.
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static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
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Opc = N->getOpcode();
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return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
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isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
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}
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// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
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// any number of 0s on either side. The 1s are allowed to wrap from LSB to
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// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
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// not, since all 1s are not contiguous.
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static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
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if (isShiftedMask_32(Val)) {
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// look for the first non-zero bit
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MB = CountLeadingZeros_32(Val);
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// look for the first zero bit after the run of ones
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ME = CountLeadingZeros_32((Val - 1) ^ Val);
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return true;
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} else if (isShiftedMask_32(Val = ~Val)) { // invert mask
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// effectively look for the first zero bit
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ME = CountLeadingZeros_32(Val) - 1;
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// effectively look for the first one bit after the run of zeros
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MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
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return true;
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}
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// no run present
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return false;
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}
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// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
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// and mask opcode and mask operation.
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static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
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unsigned &SH, unsigned &MB, unsigned &ME) {
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unsigned Shift = 32;
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unsigned Indeterminant = ~0; // bit mask marking indeterminant results
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unsigned Opcode = N->getOpcode();
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if (!isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
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return false;
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if (Opcode == ISD::SHL) {
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// apply shift left to mask if it comes first
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if (IsShiftMask) Mask = Mask << Shift;
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// determine which bits are made indeterminant by shift
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Indeterminant = ~(0xFFFFFFFFu << Shift);
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} else if (Opcode == ISD::SRA || Opcode == ISD::SRL) {
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// apply shift right to mask if it comes first
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if (IsShiftMask) Mask = Mask >> Shift;
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// determine which bits are made indeterminant by shift
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Indeterminant = ~(0xFFFFFFFFu >> Shift);
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// adjust for the left rotate
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Shift = 32 - Shift;
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} else {
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return false;
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}
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// if the mask doesn't intersect any Indeterminant bits
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if (Mask && !(Mask & Indeterminant)) {
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SH = Shift;
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// make sure the mask is still a mask (wrap arounds may not be)
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return isRunOfOnes(Mask, MB, ME);
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}
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return false;
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}
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2005-08-18 05:00:13 +00:00
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// isOpcWithIntImmediate - This method tests to see if the node is a specific
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// opcode and that it has a immediate integer right operand.
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// If so Imm will receive the 32 bit value.
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static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
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return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
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}
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// isOprNot - Returns true if the specified operand is an xor with immediate -1.
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static bool isOprNot(SDNode *N) {
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unsigned Imm;
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return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
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}
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2005-08-17 19:33:03 +00:00
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// Immediate constant composers.
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// Lo16 - grabs the lo 16 bits from a 32 bit constant.
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// Hi16 - grabs the hi 16 bits from a 32 bit constant.
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// HA16 - computes the hi bits required if the lo bits are add/subtracted in
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// arithmethically.
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static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
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static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
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static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isIntImmediate(SDOperand N, unsigned& Imm) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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Imm = (unsigned)CN->getSignExtended();
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return true;
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}
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return false;
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}
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2005-08-19 00:38:14 +00:00
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/// SelectBitfieldInsert - turn an or of two masked values into
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/// the rotate left word immediate then mask insert (rlwimi) instruction.
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/// Returns true on success, false if the caller still needs to select OR.
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///
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/// Patterns matched:
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/// 1. or shl, and 5. or and, and
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/// 2. or and, shl 6. or shl, shr
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/// 3. or shr, and 7. or shr, shl
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/// 4. or and, shr
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SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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bool IsRotate = false;
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unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
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unsigned Value;
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SDOperand Op0 = N->getOperand(0);
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SDOperand Op1 = N->getOperand(1);
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unsigned Op0Opc = Op0.getOpcode();
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unsigned Op1Opc = Op1.getOpcode();
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// Verify that we have the correct opcodes
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if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
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return false;
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if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
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return false;
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// Generate Mask value for Target
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if (isIntImmediate(Op0.getOperand(1), Value)) {
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switch(Op0Opc) {
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case ISD::SHL: TgtMask <<= Value; break;
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case ISD::SRL: TgtMask >>= Value; break;
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case ISD::AND: TgtMask &= Value; break;
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}
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} else {
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return 0;
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}
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// Generate Mask value for Insert
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if (isIntImmediate(Op1.getOperand(1), Value)) {
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switch(Op1Opc) {
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case ISD::SHL:
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SH = Value;
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InsMask <<= SH;
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if (Op0Opc == ISD::SRL) IsRotate = true;
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break;
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case ISD::SRL:
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SH = Value;
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InsMask >>= SH;
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SH = 32-SH;
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if (Op0Opc == ISD::SHL) IsRotate = true;
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break;
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case ISD::AND:
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InsMask &= Value;
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break;
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}
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} else {
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return 0;
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}
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// If both of the inputs are ANDs and one of them has a logical shift by
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// constant as its input, make that AND the inserted value so that we can
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// combine the shift into the rotate part of the rlwimi instruction
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bool IsAndWithShiftOp = false;
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if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
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if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
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Op1.getOperand(0).getOpcode() == ISD::SRL) {
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if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
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SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
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IsAndWithShiftOp = true;
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}
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} else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
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Op0.getOperand(0).getOpcode() == ISD::SRL) {
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if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
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std::swap(Op0, Op1);
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std::swap(TgtMask, InsMask);
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SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
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IsAndWithShiftOp = true;
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}
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}
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}
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// Verify that the Target mask and Insert mask together form a full word mask
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// and that the Insert mask is a run of set bits (which implies both are runs
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// of set bits). Given that, Select the arguments and generate the rlwimi
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// instruction.
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unsigned MB, ME;
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if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
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bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
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bool Op0IsAND = Op0Opc == ISD::AND;
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// Check for rotlwi / rotrwi here, a special case of bitfield insert
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// where both bitfield halves are sourced from the same value.
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if (IsRotate && fullMask &&
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N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
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Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
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Select(N->getOperand(0).getOperand(0)),
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getI32Imm(SH), getI32Imm(0), getI32Imm(31));
|
|
|
|
return Op0.Val;
|
|
|
|
}
|
|
|
|
SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
|
|
|
|
: Select(Op0);
|
|
|
|
SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
|
|
|
|
: Select(Op1.getOperand(0));
|
|
|
|
Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
|
|
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
|
|
|
|
return Op0.Val;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-08-17 19:33:03 +00:00
|
|
|
// SelectIntImmediateExpr - Choose code for integer operations with an immediate
|
|
|
|
// operand.
|
|
|
|
SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
|
|
|
|
unsigned OCHi, unsigned OCLo,
|
|
|
|
bool IsArithmetic,
|
|
|
|
bool Negate) {
|
|
|
|
// Check to make sure this is a constant.
|
|
|
|
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
|
|
|
|
// Exit if not a constant.
|
|
|
|
if (!CN) return 0;
|
|
|
|
// Extract immediate.
|
|
|
|
unsigned C = (unsigned)CN->getValue();
|
|
|
|
// Negate if required (ISD::SUB).
|
|
|
|
if (Negate) C = -C;
|
|
|
|
// Get the hi and lo portions of constant.
|
|
|
|
unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
|
|
|
|
unsigned Lo = Lo16(C);
|
|
|
|
|
|
|
|
// If two instructions are needed and usage indicates it would be better to
|
|
|
|
// load immediate into a register, bail out.
|
|
|
|
if (Hi && Lo && CN->use_size() > 2) return false;
|
|
|
|
|
|
|
|
// Select the first operand.
|
|
|
|
SDOperand Opr0 = Select(LHS);
|
|
|
|
|
|
|
|
if (Lo) // Add in the lo-part.
|
|
|
|
Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
|
|
|
|
if (Hi) // Add in the hi-part.
|
|
|
|
Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
|
|
|
|
return Opr0.Val;
|
|
|
|
}
|
|
|
|
|
2005-08-21 22:31:09 +00:00
|
|
|
/// SelectAddr - Given the specified address, return the two operands for a
|
|
|
|
/// load/store instruction, and return true if it should be an indexed [r+r]
|
|
|
|
/// operation.
|
|
|
|
bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
|
|
|
|
SDOperand &Op2) {
|
|
|
|
unsigned imm = 0;
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
|
|
if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
|
|
|
|
Op1 = getI32Imm(Lo16(imm));
|
|
|
|
if (isa<FrameIndexSDNode>(Addr.getOperand(0))) {
|
|
|
|
++FrameOff;
|
|
|
|
Op2 = Addr.getOperand(0);
|
|
|
|
} else {
|
|
|
|
Op2 = Select(Addr.getOperand(0));
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
Op1 = Select(Addr.getOperand(0));
|
|
|
|
Op2 = Select(Addr.getOperand(1));
|
|
|
|
return true; // [r+r]
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Now check if we're dealing with a global, and whether or not we should emit
|
|
|
|
// an optimized load or store for statics.
|
|
|
|
if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) {
|
|
|
|
GlobalValue *GV = GN->getGlobal();
|
|
|
|
if (!GV->hasWeakLinkage() && !GV->isExternal()) {
|
|
|
|
Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
|
|
|
|
if (PICEnabled)
|
|
|
|
Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),
|
|
|
|
Op1);
|
|
|
|
else
|
|
|
|
Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
} else if (isa<FrameIndexSDNode>(Addr)) {
|
|
|
|
Op1 = getI32Imm(0);
|
|
|
|
Op2 = Addr;
|
|
|
|
return false;
|
|
|
|
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
|
|
|
|
Op1 = Addr;
|
|
|
|
if (PICEnabled)
|
|
|
|
Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
|
|
|
|
else
|
|
|
|
Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
Op1 = getI32Imm(0);
|
|
|
|
Op2 = Select(Addr);
|
|
|
|
return false;
|
|
|
|
}
|
2005-08-17 19:33:03 +00:00
|
|
|
|
2005-08-21 18:50:37 +00:00
|
|
|
/// SelectCC - Select a comparison of the specified values with the specified
|
|
|
|
/// condition code, returning the CR# of the expression.
|
|
|
|
SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
|
|
|
|
ISD::CondCode CC) {
|
|
|
|
// Always select the LHS.
|
|
|
|
LHS = Select(LHS);
|
|
|
|
|
|
|
|
// Use U to determine whether the SETCC immediate range is signed or not.
|
|
|
|
if (MVT::isInteger(LHS.getValueType())) {
|
|
|
|
bool U = ISD::isUnsignedIntSetCC(CC);
|
|
|
|
unsigned Imm;
|
|
|
|
if (isIntImmediate(RHS, Imm) &&
|
|
|
|
((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
|
|
|
|
return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
|
|
|
|
LHS, getI32Imm(Lo16(Imm)));
|
|
|
|
return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
|
|
|
|
LHS, Select(RHS));
|
|
|
|
} else {
|
|
|
|
return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
|
|
|
|
/// to Condition.
|
|
|
|
static unsigned getBCCForSetCC(ISD::CondCode CC) {
|
|
|
|
switch (CC) {
|
|
|
|
default: assert(0 && "Unknown condition!"); abort();
|
|
|
|
case ISD::SETEQ: return PPC::BEQ;
|
|
|
|
case ISD::SETNE: return PPC::BNE;
|
|
|
|
case ISD::SETULT:
|
|
|
|
case ISD::SETLT: return PPC::BLT;
|
|
|
|
case ISD::SETULE:
|
|
|
|
case ISD::SETLE: return PPC::BLE;
|
|
|
|
case ISD::SETUGT:
|
|
|
|
case ISD::SETGT: return PPC::BGT;
|
|
|
|
case ISD::SETUGE:
|
|
|
|
case ISD::SETGE: return PPC::BGE;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-08-21 22:31:09 +00:00
|
|
|
|
2005-08-17 19:33:03 +00:00
|
|
|
// Select - Convert the specified operand from a target-independent to a
|
|
|
|
// target-specific node if it hasn't already been changed.
|
|
|
|
SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
|
|
|
SDNode *N = Op.Val;
|
|
|
|
if (N->getOpcode() >= ISD::BUILTIN_OP_END)
|
|
|
|
return Op; // Already selected.
|
|
|
|
|
|
|
|
switch (N->getOpcode()) {
|
|
|
|
default:
|
|
|
|
std::cerr << "Cannot yet select: ";
|
|
|
|
N->dump();
|
|
|
|
std::cerr << "\n";
|
|
|
|
abort();
|
|
|
|
case ISD::EntryToken: // These leaves remain the same.
|
|
|
|
case ISD::UNDEF:
|
|
|
|
return Op;
|
|
|
|
case ISD::TokenFactor: {
|
|
|
|
SDOperand New;
|
|
|
|
if (N->getNumOperands() == 2) {
|
|
|
|
SDOperand Op0 = Select(N->getOperand(0));
|
|
|
|
SDOperand Op1 = Select(N->getOperand(1));
|
|
|
|
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
|
|
|
|
} else {
|
|
|
|
std::vector<SDOperand> Ops;
|
|
|
|
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
|
2005-08-19 21:33:02 +00:00
|
|
|
Ops.push_back(Select(N->getOperand(i)));
|
2005-08-17 19:33:03 +00:00
|
|
|
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (New.Val != N) {
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, New.Val);
|
|
|
|
N = New.Val;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::CopyFromReg: {
|
|
|
|
SDOperand Chain = Select(N->getOperand(0));
|
|
|
|
if (Chain == N->getOperand(0)) return Op; // No change
|
|
|
|
SDOperand New = CurDAG->getCopyFromReg(Chain,
|
|
|
|
cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
|
|
|
|
return New.getValue(Op.ResNo);
|
|
|
|
}
|
|
|
|
case ISD::CopyToReg: {
|
|
|
|
SDOperand Chain = Select(N->getOperand(0));
|
|
|
|
SDOperand Reg = N->getOperand(1);
|
|
|
|
SDOperand Val = Select(N->getOperand(2));
|
|
|
|
if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
|
|
|
|
SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
|
|
|
|
Chain, Reg, Val);
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, New.Val);
|
|
|
|
N = New.Val;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::Constant: {
|
|
|
|
assert(N->getValueType(0) == MVT::i32);
|
|
|
|
unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
|
2005-08-18 18:01:39 +00:00
|
|
|
unsigned Hi = HA16(v);
|
|
|
|
unsigned Lo = Lo16(v);
|
|
|
|
if (Hi && Lo) {
|
|
|
|
SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
|
|
|
|
getI32Imm(v >> 16));
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
|
|
|
|
} else if (Lo) {
|
2005-08-17 19:33:03 +00:00
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
|
|
|
|
} else {
|
2005-08-18 18:01:39 +00:00
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
|
2005-08-17 19:33:03 +00:00
|
|
|
}
|
2005-08-18 18:01:39 +00:00
|
|
|
break;
|
2005-08-17 19:33:03 +00:00
|
|
|
}
|
2005-08-19 22:38:53 +00:00
|
|
|
case ISD::GlobalAddress: {
|
|
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
|
|
|
|
SDOperand Tmp;
|
|
|
|
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
|
2005-08-21 22:31:09 +00:00
|
|
|
if (PICEnabled)
|
|
|
|
Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA);
|
|
|
|
else
|
2005-08-19 22:38:53 +00:00
|
|
|
Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
|
2005-08-21 22:31:09 +00:00
|
|
|
|
2005-08-19 22:38:53 +00:00
|
|
|
if (GV->hasWeakLinkage() || GV->isExternal())
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::LWZ, GA, Tmp);
|
|
|
|
else
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::LA, Tmp, GA);
|
|
|
|
break;
|
|
|
|
}
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::SIGN_EXTEND_INREG:
|
|
|
|
switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
|
|
|
|
default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
|
|
|
|
case MVT::i16:
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSH, Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
case MVT::i8:
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSB, Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ISD::CTLZ:
|
|
|
|
assert(N->getValueType(0) == MVT::i32);
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::CNTLZW, Select(N->getOperand(0)));
|
|
|
|
break;
|
2005-08-17 19:33:03 +00:00
|
|
|
case ISD::ADD: {
|
|
|
|
MVT::ValueType Ty = N->getValueType(0);
|
|
|
|
if (Ty == MVT::i32) {
|
|
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
|
|
|
|
PPC::ADDIS, PPC::ADDI, true)) {
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, I);
|
|
|
|
N = I;
|
|
|
|
} else {
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, PPC::ADD, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!NoExcessFPPrecision) { // Match FMA ops
|
|
|
|
if (N->getOperand(0).getOpcode() == ISD::MUL &&
|
|
|
|
N->getOperand(0).Val->hasOneUse()) {
|
|
|
|
++FusedFP; // Statistic
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
|
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
Select(N->getOperand(0).getOperand(1)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
|
|
|
|
N->getOperand(1).hasOneUse()) {
|
|
|
|
++FusedFP; // Statistic
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
|
|
|
|
Select(N->getOperand(1).getOperand(0)),
|
|
|
|
Select(N->getOperand(1).getOperand(1)),
|
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS,
|
|
|
|
Select(N->getOperand(0)), Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SUB: {
|
|
|
|
MVT::ValueType Ty = N->getValueType(0);
|
|
|
|
if (Ty == MVT::i32) {
|
|
|
|
unsigned Imm;
|
|
|
|
if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
|
2005-08-24 05:03:20 +00:00
|
|
|
if (0 == Imm)
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, PPC::NEG, Select(N->getOperand(1)));
|
|
|
|
else
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, PPC::SUBFIC, Select(N->getOperand(1)),
|
|
|
|
getI32Imm(Lo16(Imm)));
|
2005-08-17 19:33:03 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
|
|
|
|
PPC::ADDIS, PPC::ADDI, true, true)) {
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, I);
|
|
|
|
N = I;
|
|
|
|
} else {
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, PPC::SUBF, Select(N->getOperand(1)),
|
|
|
|
Select(N->getOperand(0)));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!NoExcessFPPrecision) { // Match FMA ops
|
|
|
|
if (N->getOperand(0).getOpcode() == ISD::MUL &&
|
|
|
|
N->getOperand(0).Val->hasOneUse()) {
|
|
|
|
++FusedFP; // Statistic
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS,
|
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
Select(N->getOperand(0).getOperand(1)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
|
|
|
|
N->getOperand(1).Val->hasOneUse()) {
|
|
|
|
++FusedFP; // Statistic
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS,
|
|
|
|
Select(N->getOperand(1).getOperand(0)),
|
|
|
|
Select(N->getOperand(1).getOperand(1)),
|
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS,
|
|
|
|
Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
2005-08-17 23:46:35 +00:00
|
|
|
}
|
2005-08-18 00:21:41 +00:00
|
|
|
case ISD::MUL: {
|
|
|
|
unsigned Imm, Opc;
|
|
|
|
if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
|
|
|
|
CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULLI,
|
|
|
|
Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
switch (N->getValueType(0)) {
|
|
|
|
default: assert(0 && "Unhandled multiply type!");
|
|
|
|
case MVT::i32: Opc = PPC::MULLW; break;
|
|
|
|
case MVT::f32: Opc = PPC::FMULS; break;
|
|
|
|
case MVT::f64: Opc = PPC::FMUL; break;
|
|
|
|
}
|
|
|
|
CurDAG->SelectNodeTo(N, N->getValueType(0), Opc, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::MULHS:
|
2005-08-18 00:21:41 +00:00
|
|
|
assert(N->getValueType(0) == MVT::i32);
|
2005-08-18 03:04:18 +00:00
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHW, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
2005-08-18 00:21:41 +00:00
|
|
|
break;
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::MULHU:
|
2005-08-18 00:21:41 +00:00
|
|
|
assert(N->getValueType(0) == MVT::i32);
|
2005-08-18 03:04:18 +00:00
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHWU, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
2005-08-18 00:21:41 +00:00
|
|
|
break;
|
2005-08-18 07:30:46 +00:00
|
|
|
case ISD::AND: {
|
2005-08-18 18:01:39 +00:00
|
|
|
unsigned Imm;
|
2005-08-18 07:30:46 +00:00
|
|
|
// If this is an and of a value rotated between 0 and 31 bits and then and'd
|
|
|
|
// with a mask, emit rlwinm
|
|
|
|
if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
|
|
|
|
isShiftedMask_32(~Imm))) {
|
|
|
|
SDOperand Val;
|
2005-08-18 18:01:39 +00:00
|
|
|
unsigned SH, MB, ME;
|
2005-08-18 07:30:46 +00:00
|
|
|
if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
|
|
|
|
Val = Select(N->getOperand(0).getOperand(0));
|
|
|
|
} else {
|
|
|
|
Val = Select(N->getOperand(0));
|
|
|
|
isRunOfOnes(Imm, MB, ME);
|
|
|
|
SH = 0;
|
|
|
|
}
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Val, getI32Imm(SH),
|
|
|
|
getI32Imm(MB), getI32Imm(ME));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// If this is an and with an immediate that isn't a mask, then codegen it as
|
|
|
|
// high and low 16 bit immediate ands.
|
|
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
|
|
|
|
N->getOperand(1),
|
|
|
|
PPC::ANDISo, PPC::ANDIo)) {
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, I);
|
|
|
|
N = I;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Finally, check for the case where we are being asked to select
|
|
|
|
// and (not(a), b) or and (a, not(b)) which can be selected as andc.
|
|
|
|
if (isOprNot(N->getOperand(0).Val))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(1)),
|
|
|
|
Select(N->getOperand(0).getOperand(0)));
|
|
|
|
else if (isOprNot(N->getOperand(1).Val))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1).getOperand(0)));
|
|
|
|
else
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::AND, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-19 00:38:14 +00:00
|
|
|
case ISD::OR:
|
|
|
|
if (SDNode *I = SelectBitfieldInsert(N)) {
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, I);
|
|
|
|
N = I;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
|
|
|
|
N->getOperand(1),
|
|
|
|
PPC::ORIS, PPC::ORI)) {
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, I);
|
|
|
|
N = I;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Finally, check for the case where we are being asked to select
|
|
|
|
// 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
|
|
|
|
if (isOprNot(N->getOperand(0).Val))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(1)),
|
|
|
|
Select(N->getOperand(0).getOperand(0)));
|
|
|
|
else if (isOprNot(N->getOperand(1).Val))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1).getOperand(0)));
|
|
|
|
else
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::OR, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
2005-08-18 05:00:13 +00:00
|
|
|
case ISD::XOR:
|
|
|
|
// Check whether or not this node is a logical 'not'. This is represented
|
|
|
|
// by llvm as a xor with the constant value -1 (all bits set). If this is a
|
|
|
|
// 'not', then fold 'or' into 'nor', and so forth for the supported ops.
|
|
|
|
if (isOprNot(N)) {
|
|
|
|
unsigned Opc;
|
2005-08-18 05:44:50 +00:00
|
|
|
SDOperand Val = Select(N->getOperand(0));
|
|
|
|
switch (Val.getTargetOpcode()) {
|
2005-08-18 05:00:13 +00:00
|
|
|
default: Opc = 0; break;
|
2005-08-18 05:44:50 +00:00
|
|
|
case PPC::OR: Opc = PPC::NOR; break;
|
|
|
|
case PPC::AND: Opc = PPC::NAND; break;
|
|
|
|
case PPC::XOR: Opc = PPC::EQV; break;
|
2005-08-18 05:00:13 +00:00
|
|
|
}
|
|
|
|
if (Opc)
|
2005-08-18 05:44:50 +00:00
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, Opc, Val.getOperand(0),
|
|
|
|
Val.getOperand(1));
|
2005-08-18 05:00:13 +00:00
|
|
|
else
|
2005-08-18 05:44:50 +00:00
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Val, Val);
|
2005-08-18 05:00:13 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
// If this is a xor with an immediate other than -1, then codegen it as high
|
|
|
|
// and low 16 bit immediate xors.
|
|
|
|
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
|
|
|
|
N->getOperand(1),
|
|
|
|
PPC::XORIS, PPC::XORI)) {
|
|
|
|
CurDAG->ReplaceAllUsesWith(N, I);
|
|
|
|
N = I;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Finally, check for the case where we are being asked to select
|
|
|
|
// xor (not(a), b) which is equivalent to not(xor a, b), which is eqv
|
|
|
|
if (isOprNot(N->getOperand(0).Val))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::EQV,
|
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
else
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::XOR, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
2005-08-18 23:38:00 +00:00
|
|
|
case ISD::SHL: {
|
|
|
|
unsigned Imm, SH, MB, ME;
|
|
|
|
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
|
|
|
|
isRotateAndMask(N, Imm, true, SH, MB, ME))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM,
|
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
|
|
|
|
else if (isIntImmediate(N->getOperand(1), Imm))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)),
|
|
|
|
getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
|
|
|
|
else
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::SLW, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SRL: {
|
|
|
|
unsigned Imm, SH, MB, ME;
|
|
|
|
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
|
|
|
|
isRotateAndMask(N, Imm, true, SH, MB, ME))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM,
|
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
|
|
|
|
else if (isIntImmediate(N->getOperand(1), Imm))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)),
|
|
|
|
getI32Imm(32-Imm), getI32Imm(Imm), getI32Imm(31));
|
|
|
|
else
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRW, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ISD::SRA: {
|
|
|
|
unsigned Imm, SH, MB, ME;
|
|
|
|
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
|
|
|
|
isRotateAndMask(N, Imm, true, SH, MB, ME))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM,
|
|
|
|
Select(N->getOperand(0).getOperand(0)),
|
|
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
|
|
|
|
else if (isIntImmediate(N->getOperand(1), Imm))
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAWI, Select(N->getOperand(0)),
|
|
|
|
getI32Imm(Imm));
|
|
|
|
else
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAW, Select(N->getOperand(0)),
|
|
|
|
Select(N->getOperand(1)));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::FABS:
|
2005-08-18 00:53:47 +00:00
|
|
|
CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS,
|
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
2005-08-18 03:04:18 +00:00
|
|
|
case ISD::FP_EXTEND:
|
|
|
|
assert(MVT::f64 == N->getValueType(0) &&
|
|
|
|
MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::f64, PPC::FMR, Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
case ISD::FP_ROUND:
|
|
|
|
assert(MVT::f32 == N->getValueType(0) &&
|
|
|
|
MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::f32, PPC::FRSP, Select(N->getOperand(0)));
|
|
|
|
break;
|
2005-08-17 23:46:35 +00:00
|
|
|
case ISD::FNEG: {
|
|
|
|
SDOperand Val = Select(N->getOperand(0));
|
|
|
|
MVT::ValueType Ty = N->getValueType(0);
|
|
|
|
if (Val.Val->hasOneUse()) {
|
|
|
|
unsigned Opc;
|
|
|
|
switch (Val.getTargetOpcode()) {
|
|
|
|
default: Opc = 0; break;
|
|
|
|
case PPC::FABS: Opc = PPC::FNABS; break;
|
|
|
|
case PPC::FMADD: Opc = PPC::FNMADD; break;
|
|
|
|
case PPC::FMADDS: Opc = PPC::FNMADDS; break;
|
|
|
|
case PPC::FMSUB: Opc = PPC::FNMSUB; break;
|
|
|
|
case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
|
|
|
|
}
|
|
|
|
// If we inverted the opcode, then emit the new instruction with the
|
|
|
|
// inverted opcode and the original instruction's operands. Otherwise,
|
|
|
|
// fall through and generate a fneg instruction.
|
|
|
|
if (Opc) {
|
|
|
|
if (PPC::FNABS == Opc)
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0));
|
|
|
|
else
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0),
|
|
|
|
Val.getOperand(1), Val.getOperand(2));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, PPC::FNEG, Val);
|
|
|
|
break;
|
|
|
|
}
|
2005-08-18 00:53:47 +00:00
|
|
|
case ISD::FSQRT: {
|
|
|
|
MVT::ValueType Ty = N->getValueType(0);
|
|
|
|
CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS,
|
|
|
|
Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
}
|
2005-08-21 22:31:09 +00:00
|
|
|
case ISD::LOAD:
|
|
|
|
case ISD::EXTLOAD:
|
|
|
|
case ISD::ZEXTLOAD:
|
|
|
|
case ISD::SEXTLOAD: {
|
|
|
|
SDOperand Op1, Op2;
|
|
|
|
bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
|
|
|
|
|
|
|
|
MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
|
|
|
|
N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
|
|
|
|
unsigned Opc;
|
|
|
|
switch (TypeBeingLoaded) {
|
|
|
|
default: N->dump(); assert(0 && "Cannot load this type!");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
|
|
|
|
case MVT::i16:
|
|
|
|
if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
|
|
|
|
Opc = isIdx ? PPC::LHAX : PPC::LHA;
|
|
|
|
} else {
|
|
|
|
Opc = isIdx ? PPC::LHZX : PPC::LHZ;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
|
|
|
|
case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
|
|
|
|
case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
|
|
|
|
}
|
|
|
|
|
|
|
|
CurDAG->SelectNodeTo(N, N->getValueType(0), MVT::Other, Opc,
|
|
|
|
Op1, Op2, Select(N->getOperand(0)));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2005-08-22 01:27:59 +00:00
|
|
|
case ISD::TRUNCSTORE:
|
|
|
|
case ISD::STORE: {
|
|
|
|
SDOperand AddrOp1, AddrOp2;
|
|
|
|
bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
|
|
|
|
|
|
|
|
unsigned Opc;
|
|
|
|
if (N->getOpcode() == ISD::STORE) {
|
|
|
|
switch (N->getOperand(1).getValueType()) {
|
|
|
|
default: assert(0 && "unknown Type in store");
|
|
|
|
case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
|
|
|
|
case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
|
|
|
|
case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
|
|
|
|
}
|
|
|
|
} else { //ISD::TRUNCSTORE
|
|
|
|
switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
|
|
|
|
default: assert(0 && "unknown Type in store");
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
|
|
|
|
case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::Other, Opc, Select(N->getOperand(1)),
|
|
|
|
AddrOp1, AddrOp2, Select(N->getOperand(0)));
|
|
|
|
break;
|
2005-08-24 00:47:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
case ISD::CALLSEQ_START:
|
|
|
|
case ISD::CALLSEQ_END: {
|
|
|
|
unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
|
|
|
|
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
|
|
|
|
PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::Other, Opc, Select(N->getOperand(0)),
|
|
|
|
getI32Imm(Amt));
|
|
|
|
break;
|
2005-08-22 01:27:59 +00:00
|
|
|
}
|
2005-08-17 19:33:03 +00:00
|
|
|
case ISD::RET: {
|
|
|
|
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
|
|
|
|
|
|
|
|
if (N->getNumOperands() > 1) {
|
|
|
|
SDOperand Val = Select(N->getOperand(1));
|
|
|
|
switch (N->getOperand(1).getValueType()) {
|
|
|
|
default: assert(0 && "Unknown return type!");
|
|
|
|
case MVT::f64:
|
|
|
|
case MVT::f32:
|
|
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (N->getNumOperands() > 2) {
|
|
|
|
assert(N->getOperand(1).getValueType() == MVT::i32 &&
|
|
|
|
N->getOperand(2).getValueType() == MVT::i32 &&
|
|
|
|
N->getNumOperands() == 2 && "Unknown two-register ret value!");
|
|
|
|
Val = Select(N->getOperand(2));
|
|
|
|
Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Finally, select this to a blr (return) instruction.
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::Other, PPC::BLR, Chain);
|
|
|
|
break;
|
|
|
|
}
|
2005-08-21 18:50:37 +00:00
|
|
|
|
|
|
|
case ISD::BR_CC:
|
|
|
|
case ISD::BRTWOWAY_CC: {
|
|
|
|
SDOperand Chain = Select(N->getOperand(0));
|
|
|
|
MachineBasicBlock *Dest =
|
|
|
|
cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
|
|
|
|
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
|
|
|
|
unsigned Opc = getBCCForSetCC(CC);
|
|
|
|
|
|
|
|
// If this is a two way branch, then grab the fallthrough basic block
|
|
|
|
// argument and build a PowerPC branch pseudo-op, suitable for long branch
|
|
|
|
// conversion if necessary by the branch selection pass. Otherwise, emit a
|
|
|
|
// standard conditional branch.
|
|
|
|
if (N->getOpcode() == ISD::BRTWOWAY_CC) {
|
|
|
|
MachineBasicBlock *Fallthrough =
|
|
|
|
cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock();
|
|
|
|
SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
|
|
|
|
CondCode, getI32Imm(Opc),
|
|
|
|
N->getOperand(4), N->getOperand(5),
|
|
|
|
Chain);
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::Other, PPC::B, N->getOperand(5), CB);
|
|
|
|
} else {
|
|
|
|
// Iterate to the next basic block
|
|
|
|
ilist<MachineBasicBlock>::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
|
|
|
|
// If the fallthrough path is off the end of the function, which would be
|
|
|
|
// undefined behavior, set it to be the same as the current block because
|
|
|
|
// we have nothing better to set it to, and leaving it alone will cause
|
|
|
|
// the PowerPC Branch Selection pass to crash.
|
|
|
|
if (It == BB->getParent()->end()) It = Dest;
|
|
|
|
CurDAG->SelectNodeTo(N, MVT::Other, PPC::COND_BRANCH, CondCode,
|
|
|
|
getI32Imm(Opc), N->getOperand(4),
|
|
|
|
CurDAG->getBasicBlock(It), Chain);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-08-17 19:33:03 +00:00
|
|
|
}
|
2005-08-22 00:59:14 +00:00
|
|
|
return SDOperand(N, Op.ResNo);
|
2005-08-17 19:33:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/// createPPC32ISelDag - This pass converts a legalized DAG into a
|
|
|
|
/// PowerPC-specific DAG, ready for instruction scheduling.
|
|
|
|
///
|
|
|
|
FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
|
|
|
|
return new PPC32DAGToDAGISel(TM);
|
|
|
|
}
|
|
|
|
|