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llvm-6502/test/CodeGen/ARM/unaligned_load_store.ll

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Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21 05:51:33 +00:00
; RUN: llc < %s -march=arm -pre-RA-sched=source | FileCheck %s -check-prefix=GENERIC
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=DARWIN_V6
Add a command line option "-arm-strict-align" to disallow unaligned memory accesses for ARM targets that would otherwise allow it. Radar 8465431. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 04:09:35 +00:00
; RUN: llc < %s -mtriple=armv6-apple-darwin -arm-strict-align | FileCheck %s -check-prefix=GENERIC
Fix a gross typo: ARMv6+ may or may not support unaligned memory operations. Even if they are suported by the core, they can be disabled (this is just a configuration bit inside some register). Allow unaligned memops on darwin and conservatively disallow them otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-30 14:08:12 +00:00
; RUN: llc < %s -mtriple=armv6-linux | FileCheck %s -check-prefix=GENERIC
Expand unaligned loads/stores when the target doesn't support them. (PR1548) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40682 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 19:34:21 +00:00
Reapply r79127. It was fixed by d0k. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 21:21:19 +00:00
; rdar://7113725
Expand unaligned loads/stores when the target doesn't support them. (PR1548) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40682 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 19:34:21 +00:00
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 15:18:27 +00:00
define void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
Revert r79127. It was causing compilation errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79135 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 21:14:01 +00:00
entry:
Reapply r79127. It was fixed by d0k. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 21:21:19 +00:00
; GENERIC: t:
Weekly fix of register allocation dependent unit tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-30 01:37:52 +00:00
; GENERIC: ldrb [[R2:r[0-9]+]]
; GENERIC: ldrb [[R3:r[0-9]+]]
; GENERIC: ldrb [[R12:r[0-9]+]]
; GENERIC: ldrb [[R1:r[0-9]+]]
; GENERIC: strb [[R1]]
; GENERIC: strb [[R12]]
; GENERIC: strb [[R3]]
; GENERIC: strb [[R2]]
Reapply r79127. It was fixed by d0k. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79136 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-15 21:21:19 +00:00
; DARWIN_V6: t:
; DARWIN_V6: ldr r1
; DARWIN_V6: str r1
%__src1.i = bitcast i8* %b to i32* ; <i32*> [#uses=1]
%__dest2.i = bitcast i8* %a to i32* ; <i32*> [#uses=1]
%tmp.i = load i32* %__src1.i, align 1 ; <i32> [#uses=1]
store i32 %tmp.i, i32* %__dest2.i, align 1
ret void
Expand unaligned loads/stores when the target doesn't support them. (PR1548) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40682 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 19:34:21 +00:00
}
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