2007-01-19 07:51:42 +00:00
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//===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-01-19 07:51:42 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2008-09-11 21:41:29 +00:00
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// This file describes the ARM VFP instruction set.
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2007-01-19 07:51:42 +00:00
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//
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//===----------------------------------------------------------------------===//
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def SDT_FTOI :
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SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDT_ITOF :
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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def SDT_CMPFP0 :
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SDTypeProfile<0, 1, [SDTCisFP<0>]>;
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def SDT_FMDRR :
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SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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2008-11-11 02:11:05 +00:00
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def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
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def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
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def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
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def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
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2008-01-15 22:02:54 +00:00
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def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
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2008-11-11 02:11:05 +00:00
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def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
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def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
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def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
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2007-01-19 07:51:42 +00:00
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//===----------------------------------------------------------------------===//
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// Load / store Instructions.
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//
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2008-12-03 18:15:48 +00:00
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let canFoldAsLoad = 1 in {
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2008-11-11 21:48:44 +00:00
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def FLDD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
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2009-08-06 16:52:47 +00:00
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IIC_fpLoad, "fldd", " $dst, $addr",
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2007-01-19 07:51:42 +00:00
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[(set DPR:$dst, (load addrmode5:$addr))]>;
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2008-11-11 21:48:44 +00:00
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def FLDS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
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2009-08-06 16:52:47 +00:00
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IIC_fpLoad, "flds", " $dst, $addr",
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2007-01-19 07:51:42 +00:00
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[(set SPR:$dst, (load addrmode5:$addr))]>;
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2008-12-03 18:15:48 +00:00
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} // canFoldAsLoad
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2007-01-19 07:51:42 +00:00
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2008-11-11 21:48:44 +00:00
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def FSTD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
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2009-08-06 16:52:47 +00:00
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IIC_fpStore, "fstd", " $src, $addr",
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2007-01-19 07:51:42 +00:00
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[(store DPR:$src, addrmode5:$addr)]>;
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2008-11-11 21:48:44 +00:00
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def FSTS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
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2009-08-06 16:52:47 +00:00
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IIC_fpStore, "fsts", " $src, $addr",
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2007-01-19 07:51:42 +00:00
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[(store SPR:$src, addrmode5:$addr)]>;
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//===----------------------------------------------------------------------===//
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// Load / store multiple Instructions.
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//
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2008-01-10 05:12:37 +00:00
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let mayLoad = 1 in {
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
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2009-08-06 16:52:47 +00:00
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variable_ops), IIC_fpLoad,
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2007-05-29 23:34:19 +00:00
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"fldm${addr:submode}d${p} ${addr:base}, $dst1",
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2008-11-11 21:48:44 +00:00
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[]> {
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let Inst{20} = 1;
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}
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2007-01-19 07:51:42 +00:00
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
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2009-08-06 16:52:47 +00:00
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variable_ops), IIC_fpLoad,
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2007-05-29 23:34:19 +00:00
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"fldm${addr:submode}s${p} ${addr:base}, $dst1",
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2008-11-11 21:48:44 +00:00
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[]> {
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let Inst{20} = 1;
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}
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2008-01-10 05:12:37 +00:00
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}
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2007-01-19 07:51:42 +00:00
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2008-01-06 08:36:04 +00:00
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let mayStore = 1 in {
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
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2009-08-06 16:52:47 +00:00
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variable_ops), IIC_fpStore,
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2007-05-29 23:34:19 +00:00
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"fstm${addr:submode}d${p} ${addr:base}, $src1",
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2008-11-11 21:48:44 +00:00
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[]> {
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let Inst{20} = 0;
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}
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2007-01-19 07:51:42 +00:00
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
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def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
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2009-08-06 16:52:47 +00:00
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variable_ops), IIC_fpStore,
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2007-05-29 23:34:19 +00:00
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"fstm${addr:submode}s${p} ${addr:base}, $src1",
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2008-11-11 21:48:44 +00:00
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[]> {
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let Inst{20} = 0;
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}
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2008-01-06 08:36:04 +00:00
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} // mayStore
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2007-01-19 07:51:42 +00:00
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// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
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//===----------------------------------------------------------------------===//
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// FP Binary Operations.
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//
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2008-11-11 02:11:05 +00:00
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def FADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "faddd", " $dst, $a, $b",
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2007-01-19 07:51:42 +00:00
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[(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
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2009-08-04 17:53:06 +00:00
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def FADDS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fadds", " $dst, $a, $b",
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2009-08-04 17:53:06 +00:00
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[(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
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2007-01-19 07:51:42 +00:00
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2008-11-12 07:18:38 +00:00
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// These are encoded as unary instructions.
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2009-07-20 02:12:31 +00:00
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let Defs = [FPSCR] in {
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2008-11-12 07:18:38 +00:00
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def FCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a, DPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fcmped", " $a, $b",
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2008-11-12 07:18:38 +00:00
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[(arm_cmpfp DPR:$a, DPR:$b)]>;
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2007-01-19 07:51:42 +00:00
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2008-11-12 07:18:38 +00:00
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def FCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a, SPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fcmpes", " $a, $b",
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2008-11-12 07:18:38 +00:00
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[(arm_cmpfp SPR:$a, SPR:$b)]>;
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2009-07-20 02:12:31 +00:00
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}
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2007-01-19 07:51:42 +00:00
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2008-11-11 02:11:05 +00:00
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def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fdivd", " $dst, $a, $b",
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2007-01-19 07:51:42 +00:00
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[(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
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2008-11-11 02:11:05 +00:00
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def FDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fdivs", " $dst, $a, $b",
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2007-01-19 07:51:42 +00:00
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[(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
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2008-11-11 02:11:05 +00:00
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def FMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fmuld", " $dst, $a, $b",
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2007-01-19 07:51:42 +00:00
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[(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
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2009-08-04 17:53:06 +00:00
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def FMULS : ASbIn<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fmuls", " $dst, $a, $b",
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2009-08-04 17:53:06 +00:00
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[(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
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2007-05-03 00:32:00 +00:00
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2008-11-11 02:11:05 +00:00
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def FNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fnmuld", " $dst, $a, $b",
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2008-11-11 02:11:05 +00:00
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[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
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let Inst{6} = 1;
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}
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2007-01-19 07:51:42 +00:00
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2008-11-11 02:11:05 +00:00
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def FNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fnmuls", " $dst, $a, $b",
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2008-11-11 02:11:05 +00:00
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[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
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let Inst{6} = 1;
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}
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2007-01-19 07:51:42 +00:00
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2007-05-03 00:32:00 +00:00
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// Match reassociated forms only if not sign dependent rounding.
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def : Pat<(fmul (fneg DPR:$a), DPR:$b),
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(FNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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def : Pat<(fmul (fneg SPR:$a), SPR:$b),
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(FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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2008-11-11 02:11:05 +00:00
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def FSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fsubd", " $dst, $a, $b",
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2008-11-13 07:59:48 +00:00
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[(set DPR:$dst, (fsub DPR:$a, DPR:$b))]> {
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let Inst{6} = 1;
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}
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2007-01-19 07:51:42 +00:00
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2009-08-04 17:53:06 +00:00
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def FSUBS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fsubs", " $dst, $a, $b",
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2009-08-04 17:53:06 +00:00
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[(set SPR:$dst, (fsub SPR:$a, SPR:$b))]> {
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2008-11-13 07:59:48 +00:00
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let Inst{6} = 1;
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}
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2007-01-19 07:51:42 +00:00
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//===----------------------------------------------------------------------===//
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// FP Unary Operations.
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//
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2008-11-11 02:11:05 +00:00
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def FABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins DPR:$a),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fabsd", " $dst, $a",
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2007-01-19 07:51:42 +00:00
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[(set DPR:$dst, (fabs DPR:$a))]>;
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2009-08-04 20:39:05 +00:00
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def FABSS : ASuIn<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fabss", " $dst, $a",
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2009-08-04 20:39:05 +00:00
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[(set SPR:$dst, (fabs SPR:$a))]>;
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2007-01-19 07:51:42 +00:00
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2009-07-20 02:12:31 +00:00
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let Defs = [FPSCR] in {
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2008-11-11 02:11:05 +00:00
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def FCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fcmpezd", " $a",
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2007-01-19 07:51:42 +00:00
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[(arm_cmpfp0 DPR:$a)]>;
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2008-11-11 02:11:05 +00:00
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def FCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fcmpezs", " $a",
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2007-01-19 07:51:42 +00:00
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[(arm_cmpfp0 SPR:$a)]>;
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2009-07-20 02:12:31 +00:00
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}
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2007-01-19 07:51:42 +00:00
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2008-11-11 02:11:05 +00:00
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def FCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins SPR:$a),
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fcvtds", " $dst, $a",
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2007-01-19 07:51:42 +00:00
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[(set DPR:$dst, (fextend SPR:$a))]>;
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2008-11-11 02:11:05 +00:00
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// Special case encoding: bits 11-8 is 0b1011.
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2009-07-10 17:03:29 +00:00
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def FCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
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2009-08-06 16:52:47 +00:00
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IIC_fpALU, "fcvtsd", " $dst, $a",
|
2009-07-10 17:03:29 +00:00
|
|
|
[(set SPR:$dst, (fround DPR:$a))]> {
|
2008-11-11 02:11:05 +00:00
|
|
|
let Inst{27-23} = 0b11101;
|
|
|
|
let Inst{21-16} = 0b110111;
|
|
|
|
let Inst{11-8} = 0b1011;
|
|
|
|
let Inst{7-4} = 0b1100;
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2009-06-12 20:46:18 +00:00
|
|
|
let neverHasSideEffects = 1 in {
|
2008-11-11 02:11:05 +00:00
|
|
|
def FCPYD : ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins DPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fcpyd", " $dst, $a", []>;
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FCPYS : ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins SPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fcpys", " $dst, $a", []>;
|
2009-06-12 20:46:18 +00:00
|
|
|
} // neverHasSideEffects
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins DPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fnegd", " $dst, $a",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set DPR:$dst, (fneg DPR:$a))]>;
|
|
|
|
|
2009-08-04 20:39:05 +00:00
|
|
|
def FNEGS : ASuIn<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fnegs", " $dst, $a",
|
2009-08-04 20:39:05 +00:00
|
|
|
[(set SPR:$dst, (fneg SPR:$a))]>;
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fsqrtd", " $dst, $a",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set DPR:$dst, (fsqrt DPR:$a))]>;
|
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fsqrts", " $dst, $a",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set SPR:$dst, (fsqrt SPR:$a))]>;
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FP <-> GPR Copies. Int <-> FP Conversions.
|
|
|
|
//
|
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FMRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fmrs", " $dst, $src",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set GPR:$dst, (bitconvert SPR:$src))]>;
|
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FMSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fmsr", " $dst, $src",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set SPR:$dst, (bitconvert GPR:$src))]>;
|
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FMRRD : AVConv3I<0b11000101, 0b1011,
|
2008-11-11 19:40:26 +00:00
|
|
|
(outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fmrrd", " $dst1, $dst2, $src",
|
2007-01-19 07:51:42 +00:00
|
|
|
[/* FIXME: Can't write pattern for multiple result instr*/]>;
|
|
|
|
|
|
|
|
// FMDHR: GPR -> SPR
|
|
|
|
// FMDLR: GPR -> SPR
|
|
|
|
|
2008-12-11 22:02:02 +00:00
|
|
|
def FMDRR : AVConv5I<0b11000100, 0b1011,
|
|
|
|
(outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fmdrr", " $dst, $src1, $src2",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
|
|
|
|
|
|
|
|
// FMRDH: SPR -> GPR
|
|
|
|
// FMRDL: SPR -> GPR
|
|
|
|
// FMRRS: SPR -> GPR
|
|
|
|
// FMRX : SPR system reg -> GPR
|
|
|
|
|
|
|
|
// FMSRR: GPR -> SPR
|
|
|
|
|
|
|
|
// FMXR: GPR -> VFP Sstem reg
|
|
|
|
|
|
|
|
|
|
|
|
// Int to FP:
|
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fsitod", " $dst, $a",
|
2008-11-11 19:40:26 +00:00
|
|
|
[(set DPR:$dst, (arm_sitof SPR:$a))]> {
|
2008-11-15 00:40:57 +00:00
|
|
|
let Inst{7} = 1;
|
2008-11-11 19:40:26 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FSITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fsitos", " $dst, $a",
|
2008-11-11 19:40:26 +00:00
|
|
|
[(set SPR:$dst, (arm_sitof SPR:$a))]> {
|
2008-11-15 00:40:57 +00:00
|
|
|
let Inst{7} = 1;
|
2008-11-11 19:40:26 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fuitod", " $dst, $a",
|
2008-11-15 00:40:57 +00:00
|
|
|
[(set DPR:$dst, (arm_uitof SPR:$a))]>;
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FUITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fuitos", " $dst, $a",
|
2008-11-15 00:40:57 +00:00
|
|
|
[(set SPR:$dst, (arm_uitof SPR:$a))]>;
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
// FP to Int:
|
|
|
|
// Always set Z bit in the instruction, i.e. "round towards zero" variants.
|
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011,
|
2008-11-11 19:40:26 +00:00
|
|
|
(outs SPR:$dst), (ins DPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "ftosizd", " $dst, $a",
|
2008-11-11 19:40:26 +00:00
|
|
|
[(set SPR:$dst, (arm_ftosi DPR:$a))]> {
|
|
|
|
let Inst{7} = 1; // Z bit
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FTOSIZS : AVConv1I<0b11101011, 0b1101, 0b1010,
|
2008-11-11 19:40:26 +00:00
|
|
|
(outs SPR:$dst), (ins SPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "ftosizs", " $dst, $a",
|
2008-11-11 19:40:26 +00:00
|
|
|
[(set SPR:$dst, (arm_ftosi SPR:$a))]> {
|
|
|
|
let Inst{7} = 1; // Z bit
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011,
|
2008-11-11 19:40:26 +00:00
|
|
|
(outs SPR:$dst), (ins DPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "ftouizd", " $dst, $a",
|
2008-11-11 19:40:26 +00:00
|
|
|
[(set SPR:$dst, (arm_ftoui DPR:$a))]> {
|
|
|
|
let Inst{7} = 1; // Z bit
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-12 06:41:41 +00:00
|
|
|
def FTOUIZS : AVConv1I<0b11101011, 0b1100, 0b1010,
|
2008-11-11 19:40:26 +00:00
|
|
|
(outs SPR:$dst), (ins SPR:$a),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "ftouizs", " $dst, $a",
|
2008-11-11 19:40:26 +00:00
|
|
|
[(set SPR:$dst, (arm_ftoui SPR:$a))]> {
|
|
|
|
let Inst{7} = 1; // Z bit
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FP FMA Operations.
|
|
|
|
//
|
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fmacd", " $dst, $a, $b",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
2009-08-04 17:53:06 +00:00
|
|
|
def FMACS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fmacs", " $dst, $a, $b",
|
2009-08-04 17:53:06 +00:00
|
|
|
[(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fmscd", " $dst, $a, $b",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fmscs", " $dst, $a, $b",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
|
|
|
|
RegConstraint<"$dstin = $dst">;
|
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FNMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fnmacd", " $dst, $a, $b",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
|
2008-11-11 02:11:05 +00:00
|
|
|
RegConstraint<"$dstin = $dst"> {
|
|
|
|
let Inst{6} = 1;
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2009-08-04 17:53:06 +00:00
|
|
|
def FNMACS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fnmacs", " $dst, $a, $b",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
|
2008-11-11 02:11:05 +00:00
|
|
|
RegConstraint<"$dstin = $dst"> {
|
|
|
|
let Inst{6} = 1;
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2009-08-04 18:44:29 +00:00
|
|
|
def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, DPR:$b)),
|
|
|
|
(FNMACD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
|
|
|
|
def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
|
|
|
|
(FNMACS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
|
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FNMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fnmscd", " $dst, $a, $b",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
|
2008-11-11 02:11:05 +00:00
|
|
|
RegConstraint<"$dstin = $dst"> {
|
|
|
|
let Inst{6} = 1;
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-11 02:11:05 +00:00
|
|
|
def FNMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fnmscs", " $dst, $a, $b",
|
2007-01-19 07:51:42 +00:00
|
|
|
[(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
|
2008-11-11 02:11:05 +00:00
|
|
|
RegConstraint<"$dstin = $dst"> {
|
|
|
|
let Inst{6} = 1;
|
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FP Conditional moves.
|
|
|
|
//
|
|
|
|
|
2008-11-11 19:40:26 +00:00
|
|
|
def FCPYDcc : ADuI<0b11101011, 0b0000, 0b0100,
|
|
|
|
(outs DPR:$dst), (ins DPR:$false, DPR:$true),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fcpyd", " $dst, $true",
|
2007-07-05 07:13:32 +00:00
|
|
|
[/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
|
|
|
|
RegConstraint<"$false = $dst">;
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-11 19:40:26 +00:00
|
|
|
def FCPYScc : ASuI<0b11101011, 0b0000, 0b0100,
|
|
|
|
(outs SPR:$dst), (ins SPR:$false, SPR:$true),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fcpys", " $dst, $true",
|
2007-07-05 07:13:32 +00:00
|
|
|
[/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
|
|
|
|
RegConstraint<"$false = $dst">;
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-11 19:40:26 +00:00
|
|
|
def FNEGDcc : ADuI<0b11101011, 0b0001, 0b0100,
|
|
|
|
(outs DPR:$dst), (ins DPR:$false, DPR:$true),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fnegd", " $dst, $true",
|
2007-07-05 07:13:32 +00:00
|
|
|
[/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
|
|
|
|
RegConstraint<"$false = $dst">;
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2008-11-11 19:40:26 +00:00
|
|
|
def FNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
|
|
|
|
(outs SPR:$dst), (ins SPR:$false, SPR:$true),
|
2009-08-06 16:52:47 +00:00
|
|
|
IIC_fpALU, "fnegs", " $dst, $true",
|
2007-07-05 07:13:32 +00:00
|
|
|
[/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
|
|
|
|
RegConstraint<"$false = $dst">;
|
2008-11-11 19:40:26 +00:00
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Misc.
|
|
|
|
//
|
|
|
|
|
2009-07-20 02:12:31 +00:00
|
|
|
let Defs = [CPSR], Uses = [FPSCR] in
|
2009-08-06 16:52:47 +00:00
|
|
|
def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpALU, "fmstat", "", [(arm_fmstat)]> {
|
2008-11-11 21:48:44 +00:00
|
|
|
let Inst{27-20} = 0b11101111;
|
|
|
|
let Inst{19-16} = 0b0001;
|
|
|
|
let Inst{15-12} = 0b1111;
|
|
|
|
let Inst{11-8} = 0b1010;
|
|
|
|
let Inst{7} = 0;
|
|
|
|
let Inst{4} = 1;
|
|
|
|
}
|