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llvm-6502/lib/Target/ARM/Makefile

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added a skeleton of the ARM backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-14 22:18:28 +00:00
##===- lib/Target/ARM/Makefile -----------------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
remove attribution from lib Makefiles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45415 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:09:26 +00:00
# This file is distributed under the University of Illinois Open Source
added a skeleton of the ARM backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-14 22:18:28 +00:00
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
ARM backend contribution from Apple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-19 07:51:42 +00:00
added a skeleton of the ARM backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-14 22:18:28 +00:00
LEVEL = ../../..
Move ARM to pluggable asmprinter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54889 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-17 13:55:10 +00:00
LIBRARYNAME = LLVMARMCodeGen
added a skeleton of the ARM backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-14 22:18:28 +00:00
TARGET = ARM
# Make sure that tblgen is run, first thing.
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 20:07:07 +00:00
BUILT_SOURCES = ARMGenRegisterInfo.inc ARMGenInstrInfo.inc \
Starting to refactor Target to separate out code that's needed to fully describe target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 01:44:41 +00:00
ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 22:36:09 +00:00
ARMGenDAGISel.inc ARMGenSubtargetInfo.inc \
Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in ARMDecoderEmitter.cpp, with FIXME comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:53:12 +00:00
ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
Baby steps towards ARM fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 22:26:11 +00:00
ARMGenDecoderTables.inc ARMGenEDInfo.inc \
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 17:40:42 +00:00
ARMGenFastISel.inc ARMGenMCCodeEmitter.inc \
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 20:55:18 +00:00
ARMGenMCPseudoLowering.inc ARMGenDisassemblerTables.inc
added a skeleton of the ARM backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-14 22:18:28 +00:00
Add ARM MC registry routines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 22:02:34 +00:00
DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc
Move ARM to pluggable asmprinter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54889 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-17 13:55:10 +00:00
added a skeleton of the ARM backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-14 22:18:28 +00:00
include $(LEVEL)/Makefile.common
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