6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-21 00:32:23 +00:00
Code Issues Projects Releases Wiki Activity
8eabcf7ce7
llvm-6502/test/CodeGen/PowerPC/asm-constraints.ll

45 lines
1.4 KiB
LLVM
Raw Normal View History

Add missing colon to RUN line... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217623 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-11 20:13:52 +00:00
; RUN: llc < %s -mcpu=pwr8 | FileCheck %s
[PATCH, PowerPC] Accept 'U' and 'X' constraints in inline asm Inline asm may specify 'U' and 'X' constraints to print a 'u' for an update-form memory reference, or an 'x' for an indexed-form memory reference. However, these are really only useful in GCC internal code generation. In inline asm the operand of the memory constraint is typically just a register containing the address, so 'U' and 'X' make no sense. This patch quietly accepts 'U' and 'X' in inline asm patterns, but otherwise does nothing. If we ever unexpectedly see a non-register, we'll assert and sort it out afterwards. I've added a new test for these constraints; the test case should be used for other asm-constraints changes down the road. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-11 20:10:03 +00:00
Address comments on r217622 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217680 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-12 14:26:36 +00:00
; Generated from following C code:
;
; void foo (int result, char *addr) {
; __asm__ __volatile__ (
; "ld%U1%X1 %0,%1\n"
; "cmpw %0,%0\n"
; "bne- 1f\n"
; "1: isync\n"
; : "=r" (result)
; : "m"(*addr) : "memory", "cr0");
; }
[PATCH, PowerPC] Accept 'U' and 'X' constraints in inline asm Inline asm may specify 'U' and 'X' constraints to print a 'u' for an update-form memory reference, or an 'x' for an indexed-form memory reference. However, these are really only useful in GCC internal code generation. In inline asm the operand of the memory constraint is typically just a register containing the address, so 'U' and 'X' make no sense. This patch quietly accepts 'U' and 'X' in inline asm patterns, but otherwise does nothing. If we ever unexpectedly see a non-register, we'll assert and sort it out afterwards. I've added a new test for these constraints; the test case should be used for other asm-constraints changes down the road. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-11 20:10:03 +00:00
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: nounwind
; Check that we accept 'U' and 'X' constraints.
define void @foo(i32 signext %result, i8* %addr) #0 {
entry:
%result.addr = alloca i32, align 4
%addr.addr = alloca i8*, align 8
store i32 %result, i32* %result.addr, align 4
store i8* %addr, i8** %addr.addr, align 8
%0 = load i8** %addr.addr, align 8
%1 = call i32 asm sideeffect "ld${1:U}${1:X} $0,$1\0Acmpw $0,$0\0Abne- 1f\0A1: isync\0A", "=r,*m,~{memory},~{cr0}"(i8* %0) #1, !srcloc !1
store i32 %1, i32* %result.addr, align 4
ret void
}
; CHECK-LABEL: @foo
; CHECK: ld [[REG:[0-9]+]],0(4)
; CHECK-NEXT: cmpw [[REG]],[[REG]]
; CHECK-NEXT: bne- 1f
; CHECK-NEXT: 1: isync
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind }
!llvm.ident = !{!0}
!0 = metadata !{metadata !"clang version 3.6.0 (trunk 217557)"}
!1 = metadata !{i32 67, i32 91, i32 110, i32 126}
Reference in New Issue Copy Permalink