2014-05-16 17:15:33 +00:00
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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;
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; For Cortex-A53, shiftable operands that are not actually shifted
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; are not needed for an additional two cycles.
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: shiftable
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2014-06-09 01:54:00 +00:00
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; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0
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; CHECK: Successors:
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; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2
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; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2
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2014-05-16 17:15:33 +00:00
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; CHECK: ********** INTERVALS **********
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define i64 @shiftable(i64 %A, i64 %B) {
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%tmp0 = sub i64 %B, 20
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%tmp1 = shl i64 %tmp0, 5;
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%tmp2 = add i64 %A, %tmp1;
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%tmp3 = add i64 %A, %tmp0
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%tmp4 = mul i64 %tmp2, %tmp3
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ret i64 %tmp4
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}
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