2002-11-22 22:42:50 +00:00
|
|
|
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
|
2003-10-20 19:43:21 +00:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file was developed by the LLVM research group and is distributed under
|
|
|
|
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
2002-10-25 22:55:53 +00:00
|
|
|
//
|
2003-01-14 22:00:31 +00:00
|
|
|
// This file contains the X86 implementation of the TargetInstrInfo class.
|
2002-10-25 22:55:53 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2002-10-29 21:05:24 +00:00
|
|
|
#include "X86InstrInfo.h"
|
2002-12-03 05:42:53 +00:00
|
|
|
#include "X86.h"
|
2003-05-24 00:09:50 +00:00
|
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
2002-12-03 05:42:53 +00:00
|
|
|
|
2003-08-03 21:55:55 +00:00
|
|
|
#include "X86GenInstrInfo.inc"
|
2002-10-25 22:55:53 +00:00
|
|
|
|
2003-11-11 22:41:34 +00:00
|
|
|
using namespace llvm;
|
|
|
|
|
2002-10-29 21:05:24 +00:00
|
|
|
X86InstrInfo::X86InstrInfo()
|
2003-01-14 22:00:31 +00:00
|
|
|
: TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
|
2002-10-25 22:55:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2003-05-24 00:09:50 +00:00
|
|
|
// createNOPinstr - returns the target's implementation of NOP, which is
|
|
|
|
// usually a pseudo-instruction, implemented by a degenerate version of
|
|
|
|
// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
|
|
|
|
//
|
|
|
|
MachineInstr* X86InstrInfo::createNOPinstr() const {
|
2003-08-03 21:55:55 +00:00
|
|
|
return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MOTy::UseAndDef)
|
|
|
|
.addReg(X86::AX, MOTy::UseAndDef);
|
2003-05-24 00:09:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2003-05-24 01:08:43 +00:00
|
|
|
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
|
|
|
|
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
|
|
|
|
/// more than one way to `do nothing' but only one canonical way to slack off.
|
2003-05-24 00:09:50 +00:00
|
|
|
//
|
|
|
|
bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
|
|
|
|
// Make sure the instruction is EXACTLY `xchg ax, ax'
|
2003-08-03 21:55:55 +00:00
|
|
|
if (MI.getOpcode() == X86::XCHGrr16) {
|
2003-05-24 00:09:50 +00:00
|
|
|
const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
|
2004-02-10 20:31:28 +00:00
|
|
|
if (op0.isRegister() && op0.getReg() == X86::AX &&
|
|
|
|
op1.isRegister() && op1.getReg() == X86::AX) {
|
2003-05-24 00:09:50 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
2003-08-03 21:55:55 +00:00
|
|
|
// FIXME: there are several NOOP instructions, we should check for them here.
|
2003-05-24 00:09:50 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2003-12-28 17:35:08 +00:00
|
|
|
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
|
|
|
|
unsigned& sourceReg,
|
|
|
|
unsigned& destReg) const {
|
|
|
|
MachineOpCode oc = MI.getOpcode();
|
2004-02-01 08:22:16 +00:00
|
|
|
if (oc == X86::MOVrr8 || oc == X86::MOVrr16 || oc == X86::MOVrr32 ||
|
|
|
|
oc == X86::FpMOV) {
|
2003-12-28 17:35:08 +00:00
|
|
|
assert(MI.getNumOperands() == 2 &&
|
|
|
|
MI.getOperand(0).isRegister() &&
|
|
|
|
MI.getOperand(1).isRegister() &&
|
|
|
|
"invalid register-register move instruction");
|
|
|
|
sourceReg = MI.getOperand(1).getAllocatedRegNum();
|
|
|
|
destReg = MI.getOperand(0).getAllocatedRegNum();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|