2013-01-25 23:05:59 +00:00
|
|
|
//===-- PPCTargetTransformInfo.cpp - PPC specific TTI pass ----------------===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// \file
|
|
|
|
/// This file implements a TargetTransformInfo analysis pass specific to the
|
|
|
|
/// PPC target machine. It uses the target's detailed information to provide
|
|
|
|
/// more precise answers to certain TTI queries, while letting the target
|
|
|
|
/// independent and default TTI implementations handle the rest.
|
|
|
|
///
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#define DEBUG_TYPE "ppctti"
|
|
|
|
#include "PPC.h"
|
|
|
|
#include "PPCTargetMachine.h"
|
|
|
|
#include "llvm/Analysis/TargetTransformInfo.h"
|
|
|
|
#include "llvm/Support/Debug.h"
|
|
|
|
#include "llvm/Target/CostTable.h"
|
2014-01-07 11:48:04 +00:00
|
|
|
#include "llvm/Target/TargetLowering.h"
|
2013-01-25 23:05:59 +00:00
|
|
|
using namespace llvm;
|
|
|
|
|
|
|
|
// Declare the pass initialization routine locally as target-specific passes
|
|
|
|
// don't havve a target-wide initialization entry point, and so we rely on the
|
|
|
|
// pass constructor initialization.
|
|
|
|
namespace llvm {
|
|
|
|
void initializePPCTTIPass(PassRegistry &);
|
|
|
|
}
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
|
2014-03-02 08:08:51 +00:00
|
|
|
class PPCTTI final : public ImmutablePass, public TargetTransformInfo {
|
2013-01-25 23:05:59 +00:00
|
|
|
const PPCSubtarget *ST;
|
|
|
|
const PPCTargetLowering *TLI;
|
|
|
|
|
|
|
|
public:
|
2014-04-05 00:16:28 +00:00
|
|
|
PPCTTI() : ImmutablePass(ID), ST(0), TLI(0) {
|
2013-01-25 23:05:59 +00:00
|
|
|
llvm_unreachable("This pass cannot be directly constructed");
|
|
|
|
}
|
|
|
|
|
|
|
|
PPCTTI(const PPCTargetMachine *TM)
|
2014-04-05 00:16:28 +00:00
|
|
|
: ImmutablePass(ID), ST(TM->getSubtargetImpl()),
|
2013-01-25 23:05:59 +00:00
|
|
|
TLI(TM->getTargetLowering()) {
|
|
|
|
initializePPCTTIPass(*PassRegistry::getPassRegistry());
|
|
|
|
}
|
|
|
|
|
2014-03-02 09:09:27 +00:00
|
|
|
virtual void initializePass() override {
|
2013-01-25 23:05:59 +00:00
|
|
|
pushTTIStack(this);
|
|
|
|
}
|
|
|
|
|
2014-03-02 09:09:27 +00:00
|
|
|
virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
|
2013-01-25 23:05:59 +00:00
|
|
|
TargetTransformInfo::getAnalysisUsage(AU);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Pass identification.
|
|
|
|
static char ID;
|
|
|
|
|
|
|
|
/// Provide necessary pointer adjustments for the two base classes.
|
2014-03-02 09:09:27 +00:00
|
|
|
virtual void *getAdjustedAnalysisPointer(const void *ID) override {
|
2013-01-25 23:05:59 +00:00
|
|
|
if (ID == &TargetTransformInfo::ID)
|
|
|
|
return (TargetTransformInfo*)this;
|
|
|
|
return this;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// \name Scalar TTI Implementations
|
|
|
|
/// @{
|
2014-01-24 18:22:59 +00:00
|
|
|
virtual PopcntSupportKind
|
2014-03-02 09:09:27 +00:00
|
|
|
getPopcntSupport(unsigned TyWidth) const override;
|
2014-01-24 18:22:59 +00:00
|
|
|
virtual void getUnrollingPreferences(
|
2014-03-02 09:09:27 +00:00
|
|
|
Loop *L, UnrollingPreferences &UP) const override;
|
2013-01-25 23:05:59 +00:00
|
|
|
|
|
|
|
/// @}
|
|
|
|
|
|
|
|
/// \name Vector TTI Implementations
|
|
|
|
/// @{
|
|
|
|
|
2014-03-02 09:09:27 +00:00
|
|
|
virtual unsigned getNumberOfRegisters(bool Vector) const override;
|
|
|
|
virtual unsigned getRegisterBitWidth(bool Vector) const override;
|
|
|
|
virtual unsigned getMaximumUnrollFactor() const override;
|
2013-04-04 23:26:21 +00:00
|
|
|
virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
|
|
|
|
OperandValueKind,
|
2014-03-02 09:09:27 +00:00
|
|
|
OperandValueKind) const override;
|
2013-01-25 23:05:59 +00:00
|
|
|
virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
|
2014-03-02 09:09:27 +00:00
|
|
|
int Index, Type *SubTp) const override;
|
2013-01-25 23:05:59 +00:00
|
|
|
virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
|
2014-03-02 09:09:27 +00:00
|
|
|
Type *Src) const override;
|
2013-01-25 23:05:59 +00:00
|
|
|
virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
|
2014-03-02 09:09:27 +00:00
|
|
|
Type *CondTy) const override;
|
2013-01-25 23:05:59 +00:00
|
|
|
virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
|
2014-03-02 09:09:27 +00:00
|
|
|
unsigned Index) const override;
|
2013-01-25 23:05:59 +00:00
|
|
|
virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
|
|
|
|
unsigned Alignment,
|
2014-03-02 09:09:27 +00:00
|
|
|
unsigned AddressSpace) const override;
|
2013-01-25 23:05:59 +00:00
|
|
|
|
|
|
|
/// @}
|
|
|
|
};
|
|
|
|
|
|
|
|
} // end anonymous namespace
|
|
|
|
|
|
|
|
INITIALIZE_AG_PASS(PPCTTI, TargetTransformInfo, "ppctti",
|
|
|
|
"PPC Target Transform Info", true, true, false)
|
|
|
|
char PPCTTI::ID = 0;
|
|
|
|
|
|
|
|
ImmutablePass *
|
|
|
|
llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) {
|
|
|
|
return new PPCTTI(TM);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// PPC cost model.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
PPCTTI::PopcntSupportKind PPCTTI::getPopcntSupport(unsigned TyWidth) const {
|
|
|
|
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
|
2013-03-28 13:29:47 +00:00
|
|
|
if (ST->hasPOPCNTD() && TyWidth <= 64)
|
|
|
|
return PSK_FastHardware;
|
2013-01-25 23:05:59 +00:00
|
|
|
return PSK_Software;
|
|
|
|
}
|
|
|
|
|
2013-09-11 21:20:40 +00:00
|
|
|
void PPCTTI::getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const {
|
|
|
|
if (ST->getDarwinDirective() == PPC::DIR_A2) {
|
|
|
|
// The A2 is in-order with a deep pipeline, and concatenation unrolling
|
|
|
|
// helps expose latency-hiding opportunities to the instruction scheduler.
|
|
|
|
UP.Partial = UP.Runtime = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-01-25 23:05:59 +00:00
|
|
|
unsigned PPCTTI::getNumberOfRegisters(bool Vector) const {
|
|
|
|
if (Vector && !ST->hasAltivec())
|
|
|
|
return 0;
|
[PowerPC] Initial support for the VSX instruction set
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.
The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).
Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that. The assembler and disassembler
are fully implemented and tested. However:
- CodeGen support causes miscompiles; test-suite runtime failures:
MultiSource/Benchmarks/FreeBench/distray/distray
MultiSource/Benchmarks/McCat/08-main/main
MultiSource/Benchmarks/Olden/voronoi/voronoi
MultiSource/Benchmarks/mafft/pairlocalalign
MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
SingleSource/Benchmarks/CoyoteBench/almabench
SingleSource/Benchmarks/Misc/matmul_f64_4x4
- The lowering currently falls back to using Altivec instructions far more
than it should. Worse, there are some things that are scalarized through the
stack that shouldn't be.
- A lot of unnecessary copies make it past the optimizers, and this needs to
be fixed.
- Many more regression tests are needed.
Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:58:58 +00:00
|
|
|
return ST->hasVSX() ? 64 : 32;
|
2013-01-25 23:05:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PPCTTI::getRegisterBitWidth(bool Vector) const {
|
|
|
|
if (Vector) {
|
|
|
|
if (ST->hasAltivec()) return 128;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ST->isPPC64())
|
|
|
|
return 64;
|
|
|
|
return 32;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PPCTTI::getMaximumUnrollFactor() const {
|
|
|
|
unsigned Directive = ST->getDarwinDirective();
|
|
|
|
// The 440 has no SIMD support, but floating-point instructions
|
|
|
|
// have a 5-cycle latency, so unroll by 5x for latency hiding.
|
|
|
|
if (Directive == PPC::DIR_440)
|
|
|
|
return 5;
|
|
|
|
|
|
|
|
// The A2 has no SIMD support, but floating-point instructions
|
|
|
|
// have a 6-cycle latency, so unroll by 6x for latency hiding.
|
|
|
|
if (Directive == PPC::DIR_A2)
|
|
|
|
return 6;
|
|
|
|
|
|
|
|
// FIXME: For lack of any better information, do no harm...
|
|
|
|
if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
// For most things, modern systems have two execution units (and
|
|
|
|
// out-of-order execution).
|
|
|
|
return 2;
|
|
|
|
}
|
|
|
|
|
2013-04-04 23:26:21 +00:00
|
|
|
unsigned PPCTTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
|
|
|
|
OperandValueKind Op1Info,
|
|
|
|
OperandValueKind Op2Info) const {
|
2013-01-25 23:17:21 +00:00
|
|
|
assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
|
2013-01-25 23:05:59 +00:00
|
|
|
|
|
|
|
// Fallback to the default implementation.
|
2013-04-04 23:26:21 +00:00
|
|
|
return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
|
|
|
|
Op2Info);
|
2013-01-25 23:05:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PPCTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
|
|
|
|
Type *SubTp) const {
|
|
|
|
return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PPCTTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
|
2013-01-25 23:17:21 +00:00
|
|
|
assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
|
2013-01-25 23:05:59 +00:00
|
|
|
|
|
|
|
return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PPCTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
|
|
|
|
Type *CondTy) const {
|
|
|
|
return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PPCTTI::getVectorInstrCost(unsigned Opcode, Type *Val,
|
|
|
|
unsigned Index) const {
|
|
|
|
assert(Val->isVectorTy() && "This must be a vector type");
|
|
|
|
|
2013-02-08 18:19:17 +00:00
|
|
|
int ISD = TLI->InstructionOpcodeToISD(Opcode);
|
|
|
|
assert(ISD && "Invalid opcode");
|
|
|
|
|
[PowerPC] Initial support for the VSX instruction set
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.
The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).
Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that. The assembler and disassembler
are fully implemented and tested. However:
- CodeGen support causes miscompiles; test-suite runtime failures:
MultiSource/Benchmarks/FreeBench/distray/distray
MultiSource/Benchmarks/McCat/08-main/main
MultiSource/Benchmarks/Olden/voronoi/voronoi
MultiSource/Benchmarks/mafft/pairlocalalign
MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
SingleSource/Benchmarks/CoyoteBench/almabench
SingleSource/Benchmarks/Misc/matmul_f64_4x4
- The lowering currently falls back to using Altivec instructions far more
than it should. Worse, there are some things that are scalarized through the
stack that shouldn't be.
- A lot of unnecessary copies make it past the optimizers, and this needs to
be fixed.
- Many more regression tests are needed.
Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:58:58 +00:00
|
|
|
if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
|
|
|
|
// Double-precision scalars are already located in index #0.
|
|
|
|
if (Index == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
|
|
|
|
}
|
|
|
|
|
2013-02-08 18:19:17 +00:00
|
|
|
// Estimated cost of a load-hit-store delay. This was obtained
|
|
|
|
// experimentally as a minimum needed to prevent unprofitable
|
|
|
|
// vectorization for the paq8p benchmark. It may need to be
|
|
|
|
// raised further if other unprofitable cases remain.
|
2014-04-04 23:51:18 +00:00
|
|
|
unsigned LHSPenalty = 2;
|
|
|
|
if (ISD == ISD::INSERT_VECTOR_ELT)
|
|
|
|
LHSPenalty += 7;
|
2013-02-08 18:19:17 +00:00
|
|
|
|
|
|
|
// Vector element insert/extract with Altivec is very expensive,
|
|
|
|
// because they require store and reload with the attendant
|
|
|
|
// processor stall for load-hit-store. Until VSX is available,
|
|
|
|
// these need to be estimated as very costly.
|
|
|
|
if (ISD == ISD::EXTRACT_VECTOR_ELT ||
|
|
|
|
ISD == ISD::INSERT_VECTOR_ELT)
|
|
|
|
return LHSPenalty +
|
|
|
|
TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
|
2013-02-07 20:33:57 +00:00
|
|
|
|
2013-01-25 23:05:59 +00:00
|
|
|
return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
|
|
|
unsigned AddressSpace) const {
|
|
|
|
// Legalize the type.
|
|
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
|
|
|
|
assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
|
|
|
|
"Invalid Opcode");
|
|
|
|
|
2014-04-02 22:43:49 +00:00
|
|
|
unsigned Cost =
|
|
|
|
TargetTransformInfo::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
|
2013-01-25 23:05:59 +00:00
|
|
|
|
2014-04-04 23:51:18 +00:00
|
|
|
// VSX loads/stores support unaligned access.
|
|
|
|
if (ST->hasVSX()) {
|
|
|
|
if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64)
|
|
|
|
return Cost;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool UnalignedAltivec =
|
|
|
|
Src->isVectorTy() &&
|
|
|
|
Src->getPrimitiveSizeInBits() >= LT.second.getSizeInBits() &&
|
|
|
|
LT.second.getSizeInBits() == 128 &&
|
|
|
|
Opcode == Instruction::Load;
|
2014-03-26 19:39:09 +00:00
|
|
|
|
2013-01-25 23:05:59 +00:00
|
|
|
// PPC in general does not support unaligned loads and stores. They'll need
|
|
|
|
// to be decomposed based on the alignment factor.
|
|
|
|
unsigned SrcBytes = LT.second.getStoreSize();
|
2014-04-04 23:51:18 +00:00
|
|
|
if (SrcBytes && Alignment && Alignment < SrcBytes && !UnalignedAltivec) {
|
2014-04-02 22:43:49 +00:00
|
|
|
Cost += LT.first*(SrcBytes/Alignment-1);
|
2013-01-25 23:05:59 +00:00
|
|
|
|
2014-04-04 23:51:18 +00:00
|
|
|
// For a vector type, there is also scalarization overhead (only for
|
|
|
|
// stores, loads are expanded using the vector-load + permutation sequence,
|
|
|
|
// which is much less expensive).
|
|
|
|
if (Src->isVectorTy() && Opcode == Instruction::Store)
|
|
|
|
for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
|
|
|
|
Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);
|
|
|
|
}
|
|
|
|
|
2013-01-25 23:05:59 +00:00
|
|
|
return Cost;
|
|
|
|
}
|
|
|
|
|