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llvm-6502/test/MC/Disassembler/AArch64/arm64-advsimd.txt

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[ARM64] Enable feature predicates for NEON / FP / CRYPTO. AArch64 has feature predicates for NEON, FP and CRYPTO instructions. This allows the compiler to generate code without using FP, NEON or CRYPTO instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206949 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 06:22:48 +00:00
# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x00 0xb8 0x20 0x0e
0x00 0xb8 0x20 0x4e
0x00 0xb8 0x60 0x0e
0x00 0xb8 0x60 0x4e
0x00 0xb8 0xa0 0x0e
0x00 0xb8 0xa0 0x4e
# CHECK: abs.8b v0, v0
# CHECK: abs.16b v0, v0
# CHECK: abs.4h v0, v0
# CHECK: abs.8h v0, v0
# CHECK: abs.2s v0, v0
# CHECK: abs.4s v0, v0
0x00 0x84 0x20 0x0e
0x00 0x84 0x20 0x4e
0x00 0x84 0x60 0x0e
0x00 0x84 0x60 0x4e
0x00 0x84 0xa0 0x0e
0x00 0x84 0xa0 0x4e
0x00 0x84 0xe0 0x4e
# CHECK: add.8b v0, v0, v0
# CHECK: add.16b v0, v0, v0
# CHECK: add.4h v0, v0, v0
# CHECK: add.8h v0, v0, v0
# CHECK: add.2s v0, v0, v0
# CHECK: add.4s v0, v0, v0
# CHECK: add.2d v0, v0, v0
0x41 0x84 0xe3 0x5e
# CHECK: add d1, d2, d3
0x00 0x40 0x20 0x0e
0x00 0x40 0x20 0x4e
0x00 0x40 0x60 0x0e
0x00 0x40 0x60 0x4e
0x00 0x40 0xa0 0x0e
0x00 0x40 0xa0 0x4e
# CHECK: addhn.8b v0, v0, v0
# CHECK: addhn2.16b v0, v0, v0
# CHECK: addhn.4h v0, v0, v0
# CHECK: addhn2.8h v0, v0, v0
# CHECK: addhn.2s v0, v0, v0
# CHECK: addhn2.4s v0, v0, v0
0x00 0xbc 0x20 0x0e
0x00 0xbc 0x20 0x4e
0x00 0xbc 0x60 0x0e
0x00 0xbc 0x60 0x4e
0x00 0xbc 0xa0 0x0e
0x00 0xbc 0xa0 0x4e
0x00 0xbc 0xe0 0x4e
# CHECK: addp.8b v0, v0, v0
# CHECK: addp.16b v0, v0, v0
# CHECK: addp.4h v0, v0, v0
# CHECK: addp.8h v0, v0, v0
# CHECK: addp.2s v0, v0, v0
# CHECK: addp.4s v0, v0, v0
# CHECK: addp.2d v0, v0, v0
0x00 0xb8 0xf1 0x5e
# CHECK: addp.2d d0, v0
0x00 0xb8 0x31 0x0e
0x00 0xb8 0x31 0x4e
0x00 0xb8 0x71 0x0e
0x00 0xb8 0x71 0x4e
0x00 0xb8 0xb1 0x4e
# CHECK: addv.8b b0, v0
# CHECK: addv.16b b0, v0
# CHECK: addv.4h h0, v0
# CHECK: addv.8h h0, v0
# CHECK: addv.4s s0, v0
# INS/DUP
0x60 0x0c 0x08 0x4e
0x60 0x0c 0x04 0x4e
0x60 0x0c 0x04 0x0e
0x60 0x0c 0x02 0x4e
0x60 0x0c 0x02 0x0e
0x60 0x0c 0x01 0x4e
0x60 0x0c 0x01 0x0e
# CHECK: dup.2d v0, x3
# CHECK: dup.4s v0, w3
# CHECK: dup.2s v0, w3
# CHECK: dup.8h v0, w3
# CHECK: dup.4h v0, w3
# CHECK: dup.16b v0, w3
# CHECK: dup.8b v0, w3
0x60 0x04 0x18 0x4e
0x60 0x04 0x0c 0x0e
0x60 0x04 0x0c 0x4e
0x60 0x04 0x06 0x0e
0x60 0x04 0x06 0x4e
0x60 0x04 0x03 0x0e
0x60 0x04 0x03 0x4e
# CHECK: dup.2d v0, v3[1]
# CHECK: dup.2s v0, v3[1]
# CHECK: dup.4s v0, v3[1]
# CHECK: dup.4h v0, v3[1]
# CHECK: dup.8h v0, v3[1]
# CHECK: dup.8b v0, v3[1]
# CHECK: dup.16b v0, v3[1]
0x43 0x2c 0x14 0x4e
0x43 0x2c 0x14 0x4e
0x43 0x3c 0x14 0x0e
0x43 0x3c 0x14 0x0e
0x43 0x3c 0x18 0x4e
0x43 0x3c 0x18 0x4e
# CHECK: smov.s x3, v2[2]
# CHECK: smov.s x3, v2[2]
ARM64: print correct aliases for NEON mov & mvn instructions In all cases, if a "mov" alias exists, it is the canonical form of the instruction. Now that TableGen can support aliases containing syntax variants, we can enable them and improve the quality of the asm output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 12:11:02 +00:00
# CHECK: mov.s w3, v2[2]
# CHECK: mov.s w3, v2[2]
# CHECK: mov.d x3, v2[1]
# CHECK: mov.d x3, v2[1]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0xa2 0x1c 0x18 0x4e
0xa2 0x1c 0x0c 0x4e
0xa2 0x1c 0x06 0x4e
0xa2 0x1c 0x03 0x4e
0xa2 0x1c 0x18 0x4e
0xa2 0x1c 0x0c 0x4e
0xa2 0x1c 0x06 0x4e
0xa2 0x1c 0x03 0x4e
# CHECK: ins.d v2[1], x5
# CHECK: ins.s v2[1], w5
# CHECK: ins.h v2[1], w5
# CHECK: ins.b v2[1], w5
# CHECK: ins.d v2[1], x5
# CHECK: ins.s v2[1], w5
# CHECK: ins.h v2[1], w5
# CHECK: ins.b v2[1], w5
0xe2 0x45 0x18 0x6e
0xe2 0x25 0x0c 0x6e
0xe2 0x15 0x06 0x6e
0xe2 0x0d 0x03 0x6e
0xe2 0x05 0x18 0x6e
0xe2 0x45 0x1c 0x6e
0xe2 0x35 0x1e 0x6e
0xe2 0x2d 0x15 0x6e
# CHECK: ins.d v2[1], v15[1]
# CHECK: ins.s v2[1], v15[1]
# CHECK: ins.h v2[1], v15[1]
# CHECK: ins.b v2[1], v15[1]
# CHECK: ins.d v2[1], v15[0]
# CHECK: ins.s v2[3], v15[2]
# CHECK: ins.h v2[7], v15[3]
# CHECK: ins.b v2[10], v15[5]
[AArch64] Allow non-standard INS/DUP encodings The ARMv8 ARMARM states that for these instructions in A64 state: "Unspecified bits in "imm5" are ignored but should be set to zero by an assembler.", (imm4 for INS). Make the disassembler accept any encoding with these ignored bits set to 1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234896 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-14 15:07:26 +00:00
# INS/DUP (non-standard)
0x60 0x0c 0x08 0x4e
0x60 0x0c 0x0c 0x4e
0x60 0x0c 0x0c 0x0e
0x60 0x0c 0x0e 0x4e
0x60 0x0c 0x0e 0x0e
0x60 0x0c 0x0f 0x4e
0x60 0x0c 0x0f 0x0e
# CHECK: dup.2d v0, x3
# CHECK: dup.4s v0, w3
# CHECK: dup.2s v0, w3
# CHECK: dup.8h v0, w3
# CHECK: dup.4h v0, w3
# CHECK: dup.16b v0, w3
# CHECK: dup.8b v0, w3
0xe2 0x75 0x18 0x6e
0xe2 0x35 0x0c 0x6e
0xe2 0x15 0x06 0x6e
0xe2 0x0d 0x03 0x6e
0xe2 0x05 0x18 0x6e
0xe2 0x55 0x1c 0x6e
0xe2 0x35 0x1e 0x6e
0xe2 0x2d 0x15 0x6e
# CHECK: ins.d v2[1], v15[1]
# CHECK: ins.s v2[1], v15[1]
# CHECK: ins.h v2[1], v15[1]
# CHECK: ins.b v2[1], v15[1]
# CHECK: ins.d v2[1], v15[0]
# CHECK: ins.s v2[3], v15[2]
# CHECK: ins.h v2[7], v15[3]
# CHECK: ins.b v2[10], v15[5]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x00 0x1c 0x20 0x0e
0x00 0x1c 0x20 0x4e
# CHECK: and.8b v0, v0, v0
# CHECK: and.16b v0, v0, v0
0x00 0x1c 0x60 0x0e
# CHECK: bic.8b v0, v0, v0
0x00 0x8c 0x20 0x2e
0x00 0x3c 0x20 0x0e
0x00 0x34 0x20 0x0e
0x00 0x34 0x20 0x2e
0x00 0x3c 0x20 0x2e
0x00 0x8c 0x20 0x0e
0x00 0xd4 0xa0 0x2e
0x00 0xec 0x20 0x2e
0x00 0xec 0xa0 0x2e
0x00 0xd4 0x20 0x2e
0x00 0xd4 0x20 0x0e
0x00 0xe4 0x20 0x0e
0x00 0xe4 0x20 0x2e
0x00 0xe4 0xa0 0x2e
0x00 0xfc 0x20 0x2e
0x00 0xc4 0x20 0x2e
0x00 0xc4 0x20 0x0e
0x00 0xf4 0x20 0x2e
0x00 0xf4 0x20 0x0e
0x00 0xc4 0xa0 0x2e
0x00 0xc4 0xa0 0x0e
0x00 0xf4 0xa0 0x2e
0x00 0xf4 0xa0 0x0e
0x00 0xcc 0x20 0x0e
0x00 0xcc 0xa0 0x0e
0x00 0xdc 0x20 0x0e
0x00 0xdc 0x20 0x2e
0x00 0xfc 0x20 0x0e
0x00 0xfc 0xa0 0x0e
0x00 0xd4 0xa0 0x0e
0x00 0x94 0x20 0x0e
0x00 0x94 0x20 0x2e
0x00 0x9c 0x20 0x0e
0x00 0x9c 0x20 0x2e
0x00 0x7c 0x20 0x0e
0x00 0x74 0x20 0x0e
0x00 0x04 0x20 0x0e
0x00 0x24 0x20 0x0e
0x00 0xa4 0x20 0x0e
0x00 0x64 0x20 0x0e
0x00 0xac 0x20 0x0e
0x00 0x6c 0x20 0x0e
0x00 0x0c 0x20 0x0e
0x00 0xb4 0x60 0x0e
0x00 0xb4 0x60 0x2e
0x00 0x5c 0x20 0x0e
0x00 0x4c 0x20 0x0e
0x00 0x2c 0x20 0x0e
0x00 0x14 0x20 0x0e
0x00 0x54 0x20 0x0e
0x00 0x44 0x20 0x0e
0x00 0x84 0x20 0x2e
0x00 0x7c 0x20 0x2e
0x00 0x74 0x20 0x2e
0x00 0x04 0x20 0x2e
0x00 0x24 0x20 0x2e
0x00 0xa4 0x20 0x2e
0x00 0x64 0x20 0x2e
0x00 0xac 0x20 0x2e
0x00 0x6c 0x20 0x2e
0x00 0x0c 0x20 0x2e
0x00 0x5c 0x20 0x2e
0x00 0x4c 0x20 0x2e
0x00 0x2c 0x20 0x2e
0x00 0x14 0x20 0x2e
0x00 0x54 0x20 0x2e
0x00 0x44 0x20 0x2e
# CHECK: cmeq.8b v0, v0, v0
# CHECK: cmge.8b v0, v0, v0
# CHECK: cmgt.8b v0, v0, v0
# CHECK: cmhi.8b v0, v0, v0
# CHECK: cmhs.8b v0, v0, v0
# CHECK: cmtst.8b v0, v0, v0
# CHECK: fabd.2s v0, v0, v0
# CHECK: facge.2s v0, v0, v0
# CHECK: facgt.2s v0, v0, v0
# CHECK: faddp.2s v0, v0, v0
# CHECK: fadd.2s v0, v0, v0
# CHECK: fcmeq.2s v0, v0, v0
# CHECK: fcmge.2s v0, v0, v0
# CHECK: fcmgt.2s v0, v0, v0
# CHECK: fdiv.2s v0, v0, v0
# CHECK: fmaxnmp.2s v0, v0, v0
# CHECK: fmaxnm.2s v0, v0, v0
# CHECK: fmaxp.2s v0, v0, v0
# CHECK: fmax.2s v0, v0, v0
# CHECK: fminnmp.2s v0, v0, v0
# CHECK: fminnm.2s v0, v0, v0
# CHECK: fminp.2s v0, v0, v0
# CHECK: fmin.2s v0, v0, v0
# CHECK: fmla.2s v0, v0, v0
# CHECK: fmls.2s v0, v0, v0
# CHECK: fmulx.2s v0, v0, v0
# CHECK: fmul.2s v0, v0, v0
# CHECK: frecps.2s v0, v0, v0
# CHECK: frsqrts.2s v0, v0, v0
# CHECK: fsub.2s v0, v0, v0
# CHECK: mla.8b v0, v0, v0
# CHECK: mls.8b v0, v0, v0
# CHECK: mul.8b v0, v0, v0
# CHECK: pmul.8b v0, v0, v0
# CHECK: saba.8b v0, v0, v0
# CHECK: sabd.8b v0, v0, v0
# CHECK: shadd.8b v0, v0, v0
# CHECK: shsub.8b v0, v0, v0
# CHECK: smaxp.8b v0, v0, v0
# CHECK: smax.8b v0, v0, v0
# CHECK: sminp.8b v0, v0, v0
# CHECK: smin.8b v0, v0, v0
# CHECK: sqadd.8b v0, v0, v0
# CHECK: sqdmulh.4h v0, v0, v0
# CHECK: sqrdmulh.4h v0, v0, v0
# CHECK: sqrshl.8b v0, v0, v0
# CHECK: sqshl.8b v0, v0, v0
# CHECK: sqsub.8b v0, v0, v0
# CHECK: srhadd.8b v0, v0, v0
# CHECK: srshl.8b v0, v0, v0
# CHECK: sshl.8b v0, v0, v0
# CHECK: sub.8b v0, v0, v0
# CHECK: uaba.8b v0, v0, v0
# CHECK: uabd.8b v0, v0, v0
# CHECK: uhadd.8b v0, v0, v0
# CHECK: uhsub.8b v0, v0, v0
# CHECK: umaxp.8b v0, v0, v0
# CHECK: umax.8b v0, v0, v0
# CHECK: uminp.8b v0, v0, v0
# CHECK: umin.8b v0, v0, v0
# CHECK: uqadd.8b v0, v0, v0
# CHECK: uqrshl.8b v0, v0, v0
# CHECK: uqshl.8b v0, v0, v0
# CHECK: uqsub.8b v0, v0, v0
# CHECK: urhadd.8b v0, v0, v0
# CHECK: urshl.8b v0, v0, v0
# CHECK: ushl.8b v0, v0, v0
0x00 0x1c 0xe0 0x2e
0x00 0x1c 0xa0 0x2e
0x00 0x1c 0x60 0x2e
0x00 0x1c 0x20 0x2e
0x00 0x1c 0xe0 0x0e
TableGen/ARM64: print aliases even if they have syntax variants. To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208867 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 11:16:32 +00:00
0x00 0x1c 0xa1 0x0e
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
# CHECK: bif.8b v0, v0, v0
# CHECK: bit.8b v0, v0, v0
# CHECK: bsl.8b v0, v0, v0
# CHECK: eor.8b v0, v0, v0
# CHECK: orn.8b v0, v0, v0
TableGen/ARM64: print aliases even if they have syntax variants. To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208867 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 11:16:32 +00:00
# CHECK: orr.8b v0, v0, v1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x00 0x68 0x20 0x0e
0x00 0x68 0x20 0x4e
0x00 0x68 0x60 0x0e
0x00 0x68 0x60 0x4e
0x00 0x68 0xa0 0x0e
0x00 0x68 0xa0 0x4e
# CHECK: sadalp.4h v0, v0
# CHECK: sadalp.8h v0, v0
# CHECK: sadalp.2s v0, v0
# CHECK: sadalp.4s v0, v0
# CHECK: sadalp.1d v0, v0
# CHECK: sadalp.2d v0, v0
0x00 0x48 0x20 0x0e
0x00 0x48 0x20 0x2e
0x00 0x58 0x20 0x0e
0x00 0xf8 0xa0 0x0e
0x00 0xc8 0x21 0x0e
0x00 0xc8 0x21 0x2e
0x00 0xb8 0x21 0x0e
0x00 0xb8 0x21 0x2e
0x00 0xa8 0x21 0x0e
0x00 0xa8 0x21 0x2e
0x00 0xa8 0xa1 0x0e
0x00 0xa8 0xa1 0x2e
0x00 0xb8 0xa1 0x0e
0x00 0xb8 0xa1 0x2e
0x00 0xf8 0xa0 0x2e
0x00 0xd8 0xa1 0x0e
0x00 0xd8 0xa1 0x2e
0x00 0xf8 0xa1 0x2e
0x00 0xb8 0x20 0x2e
0x00 0x58 0x20 0x2e
0x00 0x58 0x60 0x2e
0x00 0x18 0x20 0x0e
0x00 0x08 0x20 0x2e
0x00 0x08 0x20 0x0e
0x00 0x68 0x20 0x0e
0x00 0x28 0x20 0x0e
0x00 0xd8 0x21 0x0e
0x00 0x38 0x21 0x2e
0x00 0x78 0x20 0x0e
0x00 0x78 0x20 0x2e
0x00 0x48 0x21 0x0e
0x00 0x28 0x21 0x2e
0x00 0x38 0x20 0x0e
0x00 0x68 0x20 0x2e
0x00 0x28 0x20 0x2e
0x00 0xd8 0x21 0x2e
0x00 0x48 0x21 0x2e
0x00 0xc8 0xa1 0x0e
0x00 0xc8 0xa1 0x2e
0x00 0x38 0x20 0x2e
0x00 0x28 0x21 0x0e
0x00 0x48 0x20 0x0e
0x00 0x48 0x20 0x2e
0x00 0x58 0x20 0x0e
0x00 0xf8 0xa0 0x0e
0x00 0xc8 0x21 0x0e
0x00 0xc8 0x21 0x2e
0x00 0xb8 0x21 0x0e
0x00 0xb8 0x21 0x2e
0x00 0xa8 0x21 0x0e
0x00 0xa8 0x21 0x2e
0x00 0xa8 0xa1 0x0e
0x00 0xa8 0xa1 0x2e
0x00 0xb8 0xa1 0x0e
0x00 0xb8 0xa1 0x2e
0x00 0xf8 0xa0 0x2e
0x00 0xd8 0xa1 0x0e
0x00 0xd8 0xa1 0x2e
0x00 0xf8 0xa1 0x2e
0x00 0xb8 0x20 0x2e
0x00 0x58 0x20 0x2e
0x00 0x58 0x60 0x2e
0x00 0x18 0x20 0x0e
0x00 0x08 0x20 0x2e
0x00 0x08 0x20 0x0e
0x00 0x68 0x20 0x0e
0x00 0x28 0x20 0x0e
0x00 0xd8 0x21 0x0e
0x00 0x38 0x21 0x2e
0x00 0x78 0x20 0x0e
0x00 0x78 0x20 0x2e
0x00 0x48 0x21 0x0e
0x00 0x28 0x21 0x2e
0x00 0x38 0x20 0x0e
0x00 0x68 0x20 0x2e
0x00 0x28 0x20 0x2e
0x00 0xd8 0x21 0x2e
0x00 0x48 0x21 0x2e
0x00 0xc8 0xa1 0x0e
0x00 0xc8 0xa1 0x2e
0x00 0x38 0x20 0x2e
0x00 0x28 0x21 0x0e
# CHECK: cls.8b v0, v0
# CHECK: clz.8b v0, v0
# CHECK: cnt.8b v0, v0
# CHECK: fabs.2s v0, v0
# CHECK: fcvtas.2s v0, v0
# CHECK: fcvtau.2s v0, v0
# CHECK: fcvtms.2s v0, v0
# CHECK: fcvtmu.2s v0, v0
# CHECK: fcvtns.2s v0, v0
# CHECK: fcvtnu.2s v0, v0
# CHECK: fcvtps.2s v0, v0
# CHECK: fcvtpu.2s v0, v0
# CHECK: fcvtzs.2s v0, v0
# CHECK: fcvtzu.2s v0, v0
# CHECK: fneg.2s v0, v0
# CHECK: frecpe.2s v0, v0
# CHECK: frsqrte.2s v0, v0
# CHECK: fsqrt.2s v0, v0
# CHECK: neg.8b v0, v0
ARM64: print correct aliases for NEON mov & mvn instructions In all cases, if a "mov" alias exists, it is the canonical form of the instruction. Now that TableGen can support aliases containing syntax variants, we can enable them and improve the quality of the asm output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 12:11:02 +00:00
# CHECK: mvn.8b v0, v0
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
# CHECK: rbit.8b v0, v0
# CHECK: rev16.8b v0, v0
# CHECK: rev32.8b v0, v0
# CHECK: rev64.8b v0, v0
# CHECK: sadalp.4h v0, v0
# CHECK: saddlp.4h v0, v0
# CHECK: scvtf.2s v0, v0
# CHECK: shll.8h v0, v0, #8
# CHECK: sqabs.8b v0, v0
# CHECK: sqneg.8b v0, v0
# CHECK: sqxtn.8b v0, v0
# CHECK: sqxtun.8b v0, v0
# CHECK: suqadd.8b v0, v0
# CHECK: uadalp.4h v0, v0
# CHECK: uaddlp.4h v0, v0
# CHECK: ucvtf.2s v0, v0
# CHECK: uqxtn.8b v0, v0
# CHECK: urecpe.2s v0, v0
# CHECK: ursqrte.2s v0, v0
# CHECK: usqadd.8b v0, v0
# CHECK: xtn.8b v0, v0
0x00 0x98 0x20 0x0e
0x00 0x98 0x20 0x4e
0x00 0x98 0x60 0x0e
0x00 0x98 0x60 0x4e
0x00 0x98 0xa0 0x0e
0x00 0x98 0xa0 0x4e
0x00 0x98 0xe0 0x4e
# CHECK: cmeq.8b v0, v0, #0
# CHECK: cmeq.16b v0, v0, #0
# CHECK: cmeq.4h v0, v0, #0
# CHECK: cmeq.8h v0, v0, #0
# CHECK: cmeq.2s v0, v0, #0
# CHECK: cmeq.4s v0, v0, #0
# CHECK: cmeq.2d v0, v0, #0
0x00 0x88 0x20 0x2e
0x00 0x88 0x20 0x0e
0x00 0x98 0x20 0x2e
0x00 0xa8 0x20 0x0e
0x00 0xd8 0xa0 0x0e
0x00 0xc8 0xa0 0x2e
0x00 0xc8 0xa0 0x0e
0x00 0xd8 0xa0 0x2e
0x00 0xe8 0xa0 0x0e
# CHECK: cmge.8b v0, v0, #0
# CHECK: cmgt.8b v0, v0, #0
# CHECK: cmle.8b v0, v0, #0
# CHECK: cmlt.8b v0, v0, #0
# CHECK: fcmeq.2s v0, v0, #0
# CHECK: fcmge.2s v0, v0, #0
# CHECK: fcmgt.2s v0, v0, #0
# CHECK: fcmle.2s v0, v0, #0
# CHECK: fcmlt.2s v0, v0, #0
0x00 0x78 0x21 0x0e
0x00 0x78 0x21 0x4e
0x00 0x78 0x61 0x0e
0x00 0x78 0x61 0x4e
0x00 0x68 0x21 0x0e
0x00 0x68 0x21 0x4e
0x00 0x68 0x61 0x0e
0x00 0x68 0x61 0x4e
0x00 0x68 0x61 0x2e
0x00 0x68 0x61 0x6e
# CHECK: fcvtl v0.4s, v0.4h
# CHECK: fcvtl2 v0.4s, v0.8h
# CHECK: fcvtl v0.2d, v0.2s
# CHECK: fcvtl2 v0.2d, v0.4s
# CHECK: fcvtn v0.4h, v0.4s
# CHECK: fcvtn2 v0.8h, v0.4s
# CHECK: fcvtn v0.2s, v0.2d
# CHECK: fcvtn2 v0.4s, v0.2d
# CHECK: fcvtxn v0.2s, v0.2d
# CHECK: fcvtxn2 v0.4s, v0.2d
#===-------------------------------------------------------------------------===
# AdvSIMD modified immediate instructions
#===-------------------------------------------------------------------------===
0x20 0x14 0x00 0x2f
0x20 0x34 0x00 0x2f
0x20 0x54 0x00 0x2f
0x20 0x74 0x00 0x2f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: bic.2s v0, #0x1
# CHECK: bic.2s v0, #0x1, lsl #8
# CHECK: bic.2s v0, #0x1, lsl #16
# CHECK: bic.2s v0, #0x1, lsl #24
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x94 0x00 0x2f
0x20 0x94 0x00 0x2f
0x20 0xb4 0x00 0x2f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: bic.4h v0, #0x1
# CHECK: bic.4h v0, #0x1
# FIXME: bic.4h v0, #0x1, lsl #8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
# 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0"
0x20 0x14 0x00 0x6f
0x20 0x34 0x00 0x6f
0x20 0x54 0x00 0x6f
0x20 0x74 0x00 0x6f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: bic.4s v0, #0x1
# CHECK: bic.4s v0, #0x1, lsl #8
# CHECK: bic.4s v0, #0x1, lsl #16
# CHECK: bic.4s v0, #0x1, lsl #24
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x94 0x00 0x6f
0x20 0xb4 0x00 0x6f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: bic.8h v0, #0x1
# FIXME: bic.8h v0, #0x1, lsl #8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
# "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0"
0x00 0xf4 0x02 0x6f
ARM64: print fp immediates without using scientific notation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:34 +00:00
# CHECK: fmov.2d v0, #0.12500000
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x00 0xf4 0x02 0x0f
0x00 0xf4 0x02 0x4f
ARM64: print fp immediates without using scientific notation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:34 +00:00
# CHECK: fmov.2s v0, #0.12500000
# CHECK: fmov.4s v0, #0.12500000
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x14 0x00 0x0f
0x20 0x34 0x00 0x0f
0x20 0x54 0x00 0x0f
0x20 0x74 0x00 0x0f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: orr.2s v0, #0x1
# CHECK: orr.2s v0, #0x1, lsl #8
# CHECK: orr.2s v0, #0x1, lsl #16
# CHECK: orr.2s v0, #0x1, lsl #24
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x94 0x00 0x0f
0x20 0xb4 0x00 0x0f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: orr.4h v0, #0x1
# FIXME: orr.4h v0, #0x1, lsl #8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
# 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0"
0x20 0x14 0x00 0x4f
0x20 0x34 0x00 0x4f
0x20 0x54 0x00 0x4f
0x20 0x74 0x00 0x4f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: orr.4s v0, #0x1
# CHECK: orr.4s v0, #0x1, lsl #8
# CHECK: orr.4s v0, #0x1, lsl #16
# CHECK: orr.4s v0, #0x1, lsl #24
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x94 0x00 0x4f
0x20 0xb4 0x00 0x4f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: orr.8h v0, #0x1
# CHECK: orr.8h v0, #0x1, lsl #8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x21 0x70 0x40 0x0c
0x42 0xa0 0x40 0x4c
0x64 0x64 0x40 0x0c
0x87 0x24 0x40 0x4c
0x0c 0xa8 0x40 0x0c
0x0a 0x68 0x40 0x4c
0x2d 0xac 0x40 0x0c
0x4f 0x7c 0x40 0x4c
[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:07 +00:00
0xe0 0x03 0x40 0x0d
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
# CHECK: ld1.8b { v1 }, [x1]
# CHECK: ld1.16b { v2, v3 }, [x2]
# CHECK: ld1.4h { v4, v5, v6 }, [x3]
# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4]
# CHECK: ld1.2s { v12, v13 }, [x0]
# CHECK: ld1.4s { v10, v11, v12 }, [x0]
# CHECK: ld1.1d { v13, v14 }, [x1]
# CHECK: ld1.2d { v15 }, [x2]
[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:44:07 +00:00
# CHECK: ld1.b { v0 }[0], [sp]
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x41 0x70 0xdf 0x0c
0x41 0xa0 0xdf 0x0c
0x41 0x60 0xdf 0x0c
0x41 0x20 0xdf 0x0c
0x42 0x70 0xdf 0x4c
0x42 0xa0 0xdf 0x4c
0x42 0x60 0xdf 0x4c
0x42 0x20 0xdf 0x4c
0x64 0x74 0xdf 0x0c
0x64 0xa4 0xdf 0x0c
0x64 0x64 0xdf 0x0c
0x64 0x24 0xdf 0x0c
0x87 0x74 0xdf 0x4c
0x87 0xa4 0xdf 0x4c
0x87 0x64 0xdf 0x4c
0x87 0x24 0xdf 0x4c
0x0c 0x78 0xdf 0x0c
0x0c 0xa8 0xdf 0x0c
0x0c 0x68 0xdf 0x0c
0x0c 0x28 0xdf 0x0c
0x0a 0x78 0xdf 0x4c
0x0a 0xa8 0xdf 0x4c
0x0a 0x68 0xdf 0x4c
0x0a 0x28 0xdf 0x4c
0x2d 0x7c 0xdf 0x0c
0x2d 0xac 0xdf 0x0c
0x2d 0x6c 0xdf 0x0c
0x2d 0x2c 0xdf 0x0c
0x4f 0x7c 0xdf 0x4c
0x4f 0xac 0xdf 0x4c
0x4f 0x6c 0xdf 0x4c
0x4f 0x2c 0xdf 0x4c
# CHECK: ld1.8b { v1 }, [x2], #8
# CHECK: ld1.8b { v1, v2 }, [x2], #16
# CHECK: ld1.8b { v1, v2, v3 }, [x2], #24
# CHECK: ld1.8b { v1, v2, v3, v4 }, [x2], #32
# CHECK: ld1.16b { v2 }, [x2], #16
# CHECK: ld1.16b { v2, v3 }, [x2], #32
# CHECK: ld1.16b { v2, v3, v4 }, [x2], #48
# CHECK: ld1.16b { v2, v3, v4, v5 }, [x2], #64
# CHECK: ld1.4h { v4 }, [x3], #8
# CHECK: ld1.4h { v4, v5 }, [x3], #16
# CHECK: ld1.4h { v4, v5, v6 }, [x3], #24
# CHECK: ld1.4h { v4, v5, v6, v7 }, [x3], #32
# CHECK: ld1.8h { v7 }, [x4], #16
# CHECK: ld1.8h { v7, v8 }, [x4], #32
# CHECK: ld1.8h { v7, v8, v9 }, [x4], #48
# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], #64
# CHECK: ld1.2s { v12 }, [x0], #8
# CHECK: ld1.2s { v12, v13 }, [x0], #16
# CHECK: ld1.2s { v12, v13, v14 }, [x0], #24
# CHECK: ld1.2s { v12, v13, v14, v15 }, [x0], #32
# CHECK: ld1.4s { v10 }, [x0], #16
# CHECK: ld1.4s { v10, v11 }, [x0], #32
# CHECK: ld1.4s { v10, v11, v12 }, [x0], #48
# CHECK: ld1.4s { v10, v11, v12, v13 }, [x0], #64
# CHECK: ld1.1d { v13 }, [x1], #8
# CHECK: ld1.1d { v13, v14 }, [x1], #16
# CHECK: ld1.1d { v13, v14, v15 }, [x1], #24
# CHECK: ld1.1d { v13, v14, v15, v16 }, [x1], #32
# CHECK: ld1.2d { v15 }, [x2], #16
# CHECK: ld1.2d { v15, v16 }, [x2], #32
# CHECK: ld1.2d { v15, v16, v17 }, [x2], #48
# CHECK: ld1.2d { v15, v16, v17, v18 }, [x2], #64
0x21 0x70 0x00 0x0c
0x42 0xa0 0x00 0x4c
0x64 0x64 0x00 0x0c
0x87 0x24 0x00 0x4c
0x0c 0xa8 0x00 0x0c
0x0a 0x68 0x00 0x4c
0x2d 0xac 0x00 0x0c
0x4f 0x7c 0x00 0x4c
# CHECK: st1.8b { v1 }, [x1]
# CHECK: st1.16b { v2, v3 }, [x2]
# CHECK: st1.4h { v4, v5, v6 }, [x3]
# CHECK: st1.8h { v7, v8, v9, v10 }, [x4]
# CHECK: st1.2s { v12, v13 }, [x0]
# CHECK: st1.4s { v10, v11, v12 }, [x0]
# CHECK: st1.1d { v13, v14 }, [x1]
# CHECK: st1.2d { v15 }, [x2]
0x61 0x08 0x40 0x0d
0x82 0x84 0x40 0x4d
0xa3 0x58 0x40 0x0d
0xc4 0x80 0x40 0x4d
# CHECK: ld1.b { v1 }[2], [x3]
# CHECK: ld1.d { v2 }[1], [x4]
# CHECK: ld1.h { v3 }[3], [x5]
# CHECK: ld1.s { v4 }[2], [x6]
0x61 0x08 0xdf 0x0d
0x82 0x84 0xdf 0x4d
0xa3 0x58 0xdf 0x0d
0xc4 0x80 0xdf 0x4d
# CHECK: ld1.b { v1 }[2], [x3], #1
# CHECK: ld1.d { v2 }[1], [x4], #8
# CHECK: ld1.h { v3 }[3], [x5], #2
# CHECK: ld1.s { v4 }[2], [x6], #4
0x61 0x08 0x00 0x0d
0x82 0x84 0x00 0x4d
0xa3 0x58 0x00 0x0d
0xc4 0x80 0x00 0x4d
# CHECK: st1.b { v1 }[2], [x3]
# CHECK: st1.d { v2 }[1], [x4]
# CHECK: st1.h { v3 }[3], [x5]
# CHECK: st1.s { v4 }[2], [x6]
0x61 0x08 0x9f 0x0d
0x82 0x84 0x9f 0x4d
0xa3 0x58 0x9f 0x0d
0xc4 0x80 0x9f 0x4d
# CHECK: st1.b { v1 }[2], [x3], #1
# CHECK: st1.d { v2 }[1], [x4], #8
# CHECK: st1.h { v3 }[3], [x5], #2
# CHECK: st1.s { v4 }[2], [x6], #4
0x61 0x08 0xc4 0x0d
0x82 0x84 0xc5 0x4d
0xa3 0x58 0xc6 0x0d
0xc4 0x80 0xc7 0x4d
# CHECK: ld1.b { v1 }[2], [x3], x4
# CHECK: ld1.d { v2 }[1], [x4], x5
# CHECK: ld1.h { v3 }[3], [x5], x6
# CHECK: ld1.s { v4 }[2], [x6], x7
0x61 0x08 0x84 0x0d
0x82 0x84 0x85 0x4d
0xa3 0x58 0x86 0x0d
0xc4 0x80 0x87 0x4d
# CHECK: st1.b { v1 }[2], [x3], x4
# CHECK: st1.d { v2 }[1], [x4], x5
# CHECK: st1.h { v3 }[3], [x5], x6
# CHECK: st1.s { v4 }[2], [x6], x7
0x41 0x70 0xc3 0x0c
0x42 0xa0 0xc4 0x4c
0x64 0x64 0xc5 0x0c
0x87 0x24 0xc6 0x4c
0x0c 0xa8 0xc7 0x0c
0x0a 0x68 0xc8 0x4c
0x2d 0xac 0xc9 0x0c
0x4f 0x7c 0xca 0x4c
# CHECK: ld1.8b { v1 }, [x2], x3
# CHECK: ld1.16b { v2, v3 }, [x2], x4
# CHECK: ld1.4h { v4, v5, v6 }, [x3], x5
# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], x6
# CHECK: ld1.2s { v12, v13 }, [x0], x7
# CHECK: ld1.4s { v10, v11, v12 }, [x0], x8
# CHECK: ld1.1d { v13, v14 }, [x1], x9
# CHECK: ld1.2d { v15 }, [x2], x10
0x41 0x70 0x83 0x0c
0x42 0xa0 0x84 0x4c
0x64 0x64 0x85 0x0c
0x87 0x24 0x86 0x4c
0x0c 0xa8 0x87 0x0c
0x0a 0x68 0x88 0x4c
0x2d 0xac 0x89 0x0c
0x4f 0x7c 0x8a 0x4c
# CHECK: st1.8b { v1 }, [x2], x3
# CHECK: st1.16b { v2, v3 }, [x2], x4
# CHECK: st1.4h { v4, v5, v6 }, [x3], x5
# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], x6
# CHECK: st1.2s { v12, v13 }, [x0], x7
# CHECK: st1.4s { v10, v11, v12 }, [x0], x8
# CHECK: st1.1d { v13, v14 }, [x1], x9
# CHECK: st1.2d { v15 }, [x2], x10
0x41 0x70 0x9f 0x0c
0x41 0xa0 0x9f 0x0c
0x41 0x60 0x9f 0x0c
0x41 0x20 0x9f 0x0c
0x42 0x70 0x9f 0x4c
0x42 0xa0 0x9f 0x4c
0x42 0x60 0x9f 0x4c
0x42 0x20 0x9f 0x4c
0x64 0x74 0x9f 0x0c
0x64 0xa4 0x9f 0x0c
0x64 0x64 0x9f 0x0c
0x64 0x24 0x9f 0x0c
0x87 0x74 0x9f 0x4c
0x87 0xa4 0x9f 0x4c
0x87 0x64 0x9f 0x4c
0x87 0x24 0x9f 0x4c
0x0c 0x78 0x9f 0x0c
0x0c 0xa8 0x9f 0x0c
0x0c 0x68 0x9f 0x0c
0x0c 0x28 0x9f 0x0c
0x0a 0x78 0x9f 0x4c
0x0a 0xa8 0x9f 0x4c
0x0a 0x68 0x9f 0x4c
0x0a 0x28 0x9f 0x4c
0x2d 0x7c 0x9f 0x0c
0x2d 0xac 0x9f 0x0c
0x2d 0x6c 0x9f 0x0c
0x2d 0x2c 0x9f 0x0c
0x4f 0x7c 0x9f 0x4c
0x4f 0xac 0x9f 0x4c
0x4f 0x6c 0x9f 0x4c
0x4f 0x2c 0x9f 0x4c
# CHECK: st1.8b { v1 }, [x2], #8
# CHECK: st1.8b { v1, v2 }, [x2], #16
# CHECK: st1.8b { v1, v2, v3 }, [x2], #24
# CHECK: st1.8b { v1, v2, v3, v4 }, [x2], #32
# CHECK: st1.16b { v2 }, [x2], #16
# CHECK: st1.16b { v2, v3 }, [x2], #32
# CHECK: st1.16b { v2, v3, v4 }, [x2], #48
# CHECK: st1.16b { v2, v3, v4, v5 }, [x2], #64
# CHECK: st1.4h { v4 }, [x3], #8
# CHECK: st1.4h { v4, v5 }, [x3], #16
# CHECK: st1.4h { v4, v5, v6 }, [x3], #24
# CHECK: st1.4h { v4, v5, v6, v7 }, [x3], #32
# CHECK: st1.8h { v7 }, [x4], #16
# CHECK: st1.8h { v7, v8 }, [x4], #32
# CHECK: st1.8h { v7, v8, v9 }, [x4], #48
# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], #64
# CHECK: st1.2s { v12 }, [x0], #8
# CHECK: st1.2s { v12, v13 }, [x0], #16
# CHECK: st1.2s { v12, v13, v14 }, [x0], #24
# CHECK: st1.2s { v12, v13, v14, v15 }, [x0], #32
# CHECK: st1.4s { v10 }, [x0], #16
# CHECK: st1.4s { v10, v11 }, [x0], #32
# CHECK: st1.4s { v10, v11, v12 }, [x0], #48
# CHECK: st1.4s { v10, v11, v12, v13 }, [x0], #64
# CHECK: st1.1d { v13 }, [x1], #8
# CHECK: st1.1d { v13, v14 }, [x1], #16
# CHECK: st1.1d { v13, v14, v15 }, [x1], #24
# CHECK: st1.1d { v13, v14, v15, v16 }, [x1], #32
# CHECK: st1.2d { v15 }, [x2], #16
# CHECK: st1.2d { v15, v16 }, [x2], #32
# CHECK: st1.2d { v15, v16, v17 }, [x2], #48
# CHECK: st1.2d { v15, v16, v17, v18 }, [x2], #64
0x21 0xc0 0x40 0x0d
0x21 0xc0 0xc2 0x0d
0x64 0xc4 0x40 0x0d
0x64 0xc4 0xc5 0x0d
0xa9 0xc8 0x40 0x0d
0xa9 0xc8 0xc6 0x0d
0xec 0xcc 0x40 0x0d
0xec 0xcc 0xc8 0x0d
# CHECK: ld1r.8b { v1 }, [x1]
# CHECK: ld1r.8b { v1 }, [x1], x2
# CHECK: ld1r.4h { v4 }, [x3]
# CHECK: ld1r.4h { v4 }, [x3], x5
# CHECK: ld1r.2s { v9 }, [x5]
# CHECK: ld1r.2s { v9 }, [x5], x6
# CHECK: ld1r.1d { v12 }, [x7]
# CHECK: ld1r.1d { v12 }, [x7], x8
0x21 0xc0 0xdf 0x0d
0x21 0xc4 0xdf 0x0d
0x21 0xc8 0xdf 0x0d
0x21 0xcc 0xdf 0x0d
# CHECK: ld1r.8b { v1 }, [x1], #1
# CHECK: ld1r.4h { v1 }, [x1], #2
# CHECK: ld1r.2s { v1 }, [x1], #4
# CHECK: ld1r.1d { v1 }, [x1], #8
0x45 0x80 0x40 0x4c
0x0a 0x88 0x40 0x0c
# CHECK: ld2.16b { v5, v6 }, [x2]
# CHECK: ld2.2s { v10, v11 }, [x0]
0x45 0x80 0x00 0x4c
0x0a 0x88 0x00 0x0c
# CHECK: st2.16b { v5, v6 }, [x2]
# CHECK: st2.2s { v10, v11 }, [x0]
0x61 0x08 0x20 0x0d
0x82 0x84 0x20 0x4d
0xc3 0x50 0x20 0x0d
0xe4 0x90 0x20 0x4d
# CHECK: st2.b { v1, v2 }[2], [x3]
# CHECK: st2.d { v2, v3 }[1], [x4]
# CHECK: st2.h { v3, v4 }[2], [x6]
# CHECK: st2.s { v4, v5 }[3], [x7]
0x61 0x08 0xbf 0x0d
0x82 0x84 0xbf 0x4d
0xa3 0x58 0xbf 0x0d
0xc4 0x80 0xbf 0x4d
# CHECK: st2.b { v1, v2 }[2], [x3], #2
# CHECK: st2.d { v2, v3 }[1], [x4], #16
# CHECK: st2.h { v3, v4 }[3], [x5], #4
# CHECK: st2.s { v4, v5 }[2], [x6], #8
0x61 0x08 0x60 0x0d
0x82 0x84 0x60 0x4d
0xc3 0x50 0x60 0x0d
0xe4 0x90 0x60 0x4d
# CHECK: ld2.b { v1, v2 }[2], [x3]
# CHECK: ld2.d { v2, v3 }[1], [x4]
# CHECK: ld2.h { v3, v4 }[2], [x6]
# CHECK: ld2.s { v4, v5 }[3], [x7]
0x61 0x08 0xff 0x0d
0x82 0x84 0xff 0x4d
0xa3 0x58 0xff 0x0d
0xc4 0x80 0xff 0x4d
# CHECK: ld2.b { v1, v2 }[2], [x3], #2
# CHECK: ld2.d { v2, v3 }[1], [x4], #16
# CHECK: ld2.h { v3, v4 }[3], [x5], #4
# CHECK: ld2.s { v4, v5 }[2], [x6], #8
0x61 0x08 0xe4 0x0d
0x82 0x84 0xe6 0x4d
0xa3 0x58 0xe8 0x0d
0xc4 0x80 0xea 0x4d
# CHECK: ld2.b { v1, v2 }[2], [x3], x4
# CHECK: ld2.d { v2, v3 }[1], [x4], x6
# CHECK: ld2.h { v3, v4 }[3], [x5], x8
# CHECK: ld2.s { v4, v5 }[2], [x6], x10
0x61 0x08 0xa4 0x0d
0x82 0x84 0xa6 0x4d
0xa3 0x58 0xa8 0x0d
0xc4 0x80 0xaa 0x4d
# CHECK: st2.b { v1, v2 }[2], [x3], x4
# CHECK: st2.d { v2, v3 }[1], [x4], x6
# CHECK: st2.h { v3, v4 }[3], [x5], x8
# CHECK: st2.s { v4, v5 }[2], [x6], x10
0x64 0x84 0xc5 0x0c
0x0c 0x88 0xc7 0x0c
# CHECK: ld2.4h { v4, v5 }, [x3], x5
# CHECK: ld2.2s { v12, v13 }, [x0], x7
0x00 0x80 0xdf 0x0c
0x00 0x80 0xdf 0x4c
0x00 0x84 0xdf 0x0c
0x00 0x84 0xdf 0x4c
0x00 0x88 0xdf 0x0c
0x00 0x88 0xdf 0x4c
0x00 0x8c 0xdf 0x4c
# CHECK: ld2.8b { v0, v1 }, [x0], #16
# CHECK: ld2.16b { v0, v1 }, [x0], #32
# CHECK: ld2.4h { v0, v1 }, [x0], #16
# CHECK: ld2.8h { v0, v1 }, [x0], #32
# CHECK: ld2.2s { v0, v1 }, [x0], #16
# CHECK: ld2.4s { v0, v1 }, [x0], #32
# CHECK: ld2.2d { v0, v1 }, [x0], #32
0x64 0x84 0x85 0x0c
0x0c 0x88 0x87 0x0c
# CHECK: st2.4h { v4, v5 }, [x3], x5
# CHECK: st2.2s { v12, v13 }, [x0], x7
0x00 0x80 0x9f 0x0c
0x00 0x80 0x9f 0x4c
0x00 0x84 0x9f 0x0c
0x00 0x84 0x9f 0x4c
0x00 0x88 0x9f 0x0c
0x00 0x88 0x9f 0x4c
0x00 0x8c 0x9f 0x4c
# CHECK: st2.8b { v0, v1 }, [x0], #16
# CHECK: st2.16b { v0, v1 }, [x0], #32
# CHECK: st2.4h { v0, v1 }, [x0], #16
# CHECK: st2.8h { v0, v1 }, [x0], #32
# CHECK: st2.2s { v0, v1 }, [x0], #16
# CHECK: st2.4s { v0, v1 }, [x0], #32
# CHECK: st2.2d { v0, v1 }, [x0], #32
0x21 0xc0 0x60 0x0d
0x21 0xc0 0xe2 0x0d
0x21 0xc0 0x60 0x4d
0x21 0xc0 0xe2 0x4d
0x21 0xc4 0x60 0x0d
0x21 0xc4 0xe2 0x0d
0x21 0xc4 0x60 0x4d
0x21 0xc4 0xe2 0x4d
0x21 0xc8 0x60 0x0d
0x21 0xc8 0xe2 0x0d
0x21 0xcc 0x60 0x4d
0x21 0xcc 0xe2 0x4d
0x21 0xcc 0x60 0x0d
0x21 0xcc 0xe2 0x0d
# CHECK: ld2r.8b { v1, v2 }, [x1]
# CHECK: ld2r.8b { v1, v2 }, [x1], x2
# CHECK: ld2r.16b { v1, v2 }, [x1]
# CHECK: ld2r.16b { v1, v2 }, [x1], x2
# CHECK: ld2r.4h { v1, v2 }, [x1]
# CHECK: ld2r.4h { v1, v2 }, [x1], x2
# CHECK: ld2r.8h { v1, v2 }, [x1]
# CHECK: ld2r.8h { v1, v2 }, [x1], x2
# CHECK: ld2r.2s { v1, v2 }, [x1]
# CHECK: ld2r.2s { v1, v2 }, [x1], x2
# CHECK: ld2r.2d { v1, v2 }, [x1]
# CHECK: ld2r.2d { v1, v2 }, [x1], x2
# CHECK: ld2r.1d { v1, v2 }, [x1]
# CHECK: ld2r.1d { v1, v2 }, [x1], x2
0x21 0xc0 0xff 0x0d
0x21 0xc0 0xff 0x4d
0x21 0xc4 0xff 0x0d
0x21 0xc4 0xff 0x4d
0x21 0xc8 0xff 0x0d
0x21 0xcc 0xff 0x4d
0x21 0xcc 0xff 0x0d
# CHECK: ld2r.8b { v1, v2 }, [x1], #2
# CHECK: ld2r.16b { v1, v2 }, [x1], #2
# CHECK: ld2r.4h { v1, v2 }, [x1], #4
# CHECK: ld2r.8h { v1, v2 }, [x1], #4
# CHECK: ld2r.2s { v1, v2 }, [x1], #8
# CHECK: ld2r.2d { v1, v2 }, [x1], #16
# CHECK: ld2r.1d { v1, v2 }, [x1], #16
0x21 0x40 0x40 0x0c
0x45 0x40 0x40 0x4c
0x0a 0x48 0x40 0x0c
# CHECK: ld3.8b { v1, v2, v3 }, [x1]
# CHECK: ld3.16b { v5, v6, v7 }, [x2]
# CHECK: ld3.2s { v10, v11, v12 }, [x0]
0x21 0x40 0x00 0x0c
0x45 0x40 0x00 0x4c
0x0a 0x48 0x00 0x0c
# CHECK: st3.8b { v1, v2, v3 }, [x1]
# CHECK: st3.16b { v5, v6, v7 }, [x2]
# CHECK: st3.2s { v10, v11, v12 }, [x0]
0x61 0x28 0xc4 0x0d
0x82 0xa4 0xc5 0x4d
0xa3 0x78 0xc6 0x0d
0xc4 0xa0 0xc7 0x4d
# CHECK: ld3.b { v1, v2, v3 }[2], [x3], x4
# CHECK: ld3.d { v2, v3, v4 }[1], [x4], x5
# CHECK: ld3.h { v3, v4, v5 }[3], [x5], x6
# CHECK: ld3.s { v4, v5, v6 }[2], [x6], x7
0x61 0x28 0x84 0x0d
0x82 0xa4 0x85 0x4d
0xa3 0x78 0x86 0x0d
0xc4 0xa0 0x87 0x4d
# CHECK: st3.b { v1, v2, v3 }[2], [x3], x4
# CHECK: st3.d { v2, v3, v4 }[1], [x4], x5
# CHECK: st3.h { v3, v4, v5 }[3], [x5], x6
# CHECK: st3.s { v4, v5, v6 }[2], [x6], x7
0x61 0x28 0x9f 0x0d
0x82 0xa4 0x9f 0x4d
0xa3 0x78 0x9f 0x0d
0xc4 0xa0 0x9f 0x4d
# CHECK: st3.b { v1, v2, v3 }[2], [x3], #3
# CHECK: st3.d { v2, v3, v4 }[1], [x4], #24
# CHECK: st3.h { v3, v4, v5 }[3], [x5], #6
# CHECK: st3.s { v4, v5, v6 }[2], [x6], #12
0x41 0x40 0xc3 0x0c
0x42 0x40 0xc4 0x4c
0x64 0x44 0xc5 0x0c
0x87 0x44 0xc6 0x4c
0x0c 0x48 0xc7 0x0c
0x0a 0x48 0xc8 0x4c
0x4f 0x4c 0xca 0x4c
# CHECK: ld3.8b { v1, v2, v3 }, [x2], x3
# CHECK: ld3.16b { v2, v3, v4 }, [x2], x4
# CHECK: ld3.4h { v4, v5, v6 }, [x3], x5
# CHECK: ld3.8h { v7, v8, v9 }, [x4], x6
# CHECK: ld3.2s { v12, v13, v14 }, [x0], x7
# CHECK: ld3.4s { v10, v11, v12 }, [x0], x8
# CHECK: ld3.2d { v15, v16, v17 }, [x2], x10
0x00 0x40 0xdf 0x0c
0x00 0x40 0xdf 0x4c
0x00 0x44 0xdf 0x0c
0x00 0x44 0xdf 0x4c
0x00 0x48 0xdf 0x0c
0x00 0x48 0xdf 0x4c
0x00 0x4c 0xdf 0x4c
# CHECK: ld3.8b { v0, v1, v2 }, [x0], #24
# CHECK: ld3.16b { v0, v1, v2 }, [x0], #48
# CHECK: ld3.4h { v0, v1, v2 }, [x0], #24
# CHECK: ld3.8h { v0, v1, v2 }, [x0], #48
# CHECK: ld3.2s { v0, v1, v2 }, [x0], #24
# CHECK: ld3.4s { v0, v1, v2 }, [x0], #48
# CHECK: ld3.2d { v0, v1, v2 }, [x0], #48
0x41 0x40 0x83 0x0c
0x42 0x40 0x84 0x4c
0x64 0x44 0x85 0x0c
0x87 0x44 0x86 0x4c
0x0c 0x48 0x87 0x0c
0x0a 0x48 0x88 0x4c
0x4f 0x4c 0x8a 0x4c
# CHECK: st3.8b { v1, v2, v3 }, [x2], x3
# CHECK: st3.16b { v2, v3, v4 }, [x2], x4
# CHECK: st3.4h { v4, v5, v6 }, [x3], x5
# CHECK: st3.8h { v7, v8, v9 }, [x4], x6
# CHECK: st3.2s { v12, v13, v14 }, [x0], x7
# CHECK: st3.4s { v10, v11, v12 }, [x0], x8
# CHECK: st3.2d { v15, v16, v17 }, [x2], x10
0x00 0x40 0x9f 0x0c
0x00 0x40 0x9f 0x4c
0x00 0x44 0x9f 0x0c
0x00 0x44 0x9f 0x4c
0x00 0x48 0x9f 0x0c
0x00 0x48 0x9f 0x4c
0x00 0x4c 0x9f 0x4c
# CHECK: st3.8b { v0, v1, v2 }, [x0], #24
# CHECK: st3.16b { v0, v1, v2 }, [x0], #48
# CHECK: st3.4h { v0, v1, v2 }, [x0], #24
# CHECK: st3.8h { v0, v1, v2 }, [x0], #48
# CHECK: st3.2s { v0, v1, v2 }, [x0], #24
# CHECK: st3.4s { v0, v1, v2 }, [x0], #48
# CHECK: st3.2d { v0, v1, v2 }, [x0], #48
0x61 0x28 0x40 0x0d
0x82 0xa4 0x40 0x4d
0xc3 0x70 0x40 0x0d
0xe4 0xb0 0x40 0x4d
# CHECK: ld3.b { v1, v2, v3 }[2], [x3]
# CHECK: ld3.d { v2, v3, v4 }[1], [x4]
# CHECK: ld3.h { v3, v4, v5 }[2], [x6]
# CHECK: ld3.s { v4, v5, v6 }[3], [x7]
0x61 0x28 0xdf 0x0d
0x82 0xa4 0xdf 0x4d
0xa3 0x78 0xdf 0x0d
0xc4 0xa0 0xdf 0x4d
# CHECK: ld3.b { v1, v2, v3 }[2], [x3], #3
# CHECK: ld3.d { v2, v3, v4 }[1], [x4], #24
# CHECK: ld3.h { v3, v4, v5 }[3], [x5], #6
# CHECK: ld3.s { v4, v5, v6 }[2], [x6], #12
0x61 0x28 0x00 0x0d
0x82 0xa4 0x00 0x4d
0xc3 0x70 0x00 0x0d
0xe4 0xb0 0x00 0x4d
# CHECK: st3.b { v1, v2, v3 }[2], [x3]
# CHECK: st3.d { v2, v3, v4 }[1], [x4]
# CHECK: st3.h { v3, v4, v5 }[2], [x6]
# CHECK: st3.s { v4, v5, v6 }[3], [x7]
0x21 0xe0 0x40 0x0d
0x21 0xe0 0xc2 0x0d
0x21 0xe0 0x40 0x4d
0x21 0xe0 0xc2 0x4d
0x21 0xe4 0x40 0x0d
0x21 0xe4 0xc2 0x0d
0x21 0xe4 0x40 0x4d
0x21 0xe4 0xc2 0x4d
0x21 0xe8 0x40 0x0d
0x21 0xe8 0xc2 0x0d
0x21 0xec 0x40 0x4d
0x21 0xec 0xc2 0x4d
0x21 0xec 0x40 0x0d
0x21 0xec 0xc2 0x0d
# CHECK: ld3r.8b { v1, v2, v3 }, [x1]
# CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2
# CHECK: ld3r.16b { v1, v2, v3 }, [x1]
# CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2
# CHECK: ld3r.4h { v1, v2, v3 }, [x1]
# CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2
# CHECK: ld3r.8h { v1, v2, v3 }, [x1]
# CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2
# CHECK: ld3r.2s { v1, v2, v3 }, [x1]
# CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2
# CHECK: ld3r.2d { v1, v2, v3 }, [x1]
# CHECK: ld3r.2d { v1, v2, v3 }, [x1], x2
# CHECK: ld3r.1d { v1, v2, v3 }, [x1]
# CHECK: ld3r.1d { v1, v2, v3 }, [x1], x2
0x21 0xe0 0xdf 0x0d
0x21 0xe0 0xdf 0x4d
0x21 0xe4 0xdf 0x0d
0x21 0xe4 0xdf 0x4d
0x21 0xe8 0xdf 0x0d
0x21 0xec 0xdf 0x4d
0x21 0xec 0xdf 0x0d
# CHECK: ld3r.8b { v1, v2, v3 }, [x1], #3
# CHECK: ld3r.16b { v1, v2, v3 }, [x1], #3
# CHECK: ld3r.4h { v1, v2, v3 }, [x1], #6
# CHECK: ld3r.8h { v1, v2, v3 }, [x1], #6
# CHECK: ld3r.2s { v1, v2, v3 }, [x1], #12
# CHECK: ld3r.2d { v1, v2, v3 }, [x1], #24
# CHECK: ld3r.1d { v1, v2, v3 }, [x1], #24
0x21 0x00 0x40 0x0c
0x45 0x00 0x40 0x4c
0x0a 0x08 0x40 0x0c
# CHECK: ld4.8b { v1, v2, v3, v4 }, [x1]
# CHECK: ld4.16b { v5, v6, v7, v8 }, [x2]
# CHECK: ld4.2s { v10, v11, v12, v13 }, [x0]
0x21 0x00 0x00 0x0c
0x45 0x00 0x00 0x4c
0x0a 0x08 0x00 0x0c
# CHECK: st4.8b { v1, v2, v3, v4 }, [x1]
# CHECK: st4.16b { v5, v6, v7, v8 }, [x2]
# CHECK: st4.2s { v10, v11, v12, v13 }, [x0]
0x61 0x28 0xe4 0x0d
0x82 0xa4 0xe5 0x4d
0xa3 0x78 0xe6 0x0d
0xc4 0xa0 0xe7 0x4d
# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], x4
# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], x5
# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], x6
# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], x7
0x61 0x28 0xff 0x0d
0x82 0xa4 0xff 0x4d
0xa3 0x78 0xff 0x0d
0xc4 0xa0 0xff 0x4d
# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], #4
# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], #32
# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], #8
# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], #16
0x61 0x28 0xa4 0x0d
0x82 0xa4 0xa5 0x4d
0xa3 0x78 0xa6 0x0d
0xc4 0xa0 0xa7 0x4d
# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], x4
# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], x5
# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], x6
# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], x7
0x61 0x28 0xbf 0x0d
0x82 0xa4 0xbf 0x4d
0xa3 0x78 0xbf 0x0d
0xc4 0xa0 0xbf 0x4d
# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], #4
# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], #32
# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], #8
# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], #16
0x41 0x00 0xc3 0x0c
0x42 0x00 0xc4 0x4c
0x64 0x04 0xc5 0x0c
0x87 0x04 0xc6 0x4c
0x0c 0x08 0xc7 0x0c
0x0a 0x08 0xc8 0x4c
0x4f 0x0c 0xca 0x4c
# CHECK: ld4.8b { v1, v2, v3, v4 }, [x2], x3
# CHECK: ld4.16b { v2, v3, v4, v5 }, [x2], x4
# CHECK: ld4.4h { v4, v5, v6, v7 }, [x3], x5
# CHECK: ld4.8h { v7, v8, v9, v10 }, [x4], x6
# CHECK: ld4.2s { v12, v13, v14, v15 }, [x0], x7
# CHECK: ld4.4s { v10, v11, v12, v13 }, [x0], x8
# CHECK: ld4.2d { v15, v16, v17, v18 }, [x2], x10
0x00 0x00 0xdf 0x0c
0x00 0x00 0xdf 0x4c
0x00 0x04 0xdf 0x0c
0x00 0x04 0xdf 0x4c
0x00 0x08 0xdf 0x0c
0x00 0x08 0xdf 0x4c
0x00 0x0c 0xdf 0x4c
# CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32
# CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64
# CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], #32
# CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], #64
# CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32
# CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64
# CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64
0x00 0x00 0x9f 0x0c
0x00 0x00 0x9f 0x4c
0x00 0x04 0x9f 0x0c
0x00 0x04 0x9f 0x4c
0x00 0x08 0x9f 0x0c
0x00 0x08 0x9f 0x4c
0x00 0x0c 0x9f 0x4c
# CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32
# CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64
# CHECK: st4.4h { v0, v1, v2, v3 }, [x0], #32
# CHECK: st4.8h { v0, v1, v2, v3 }, [x0], #64
# CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32
# CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64
# CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64
0x41 0x00 0x83 0x0c
0x42 0x00 0x84 0x4c
0x64 0x04 0x85 0x0c
0x87 0x04 0x86 0x4c
0x0c 0x08 0x87 0x0c
0x0a 0x08 0x88 0x4c
0x4f 0x0c 0x8a 0x4c
# CHECK: st4.8b { v1, v2, v3, v4 }, [x2], x3
# CHECK: st4.16b { v2, v3, v4, v5 }, [x2], x4
# CHECK: st4.4h { v4, v5, v6, v7 }, [x3], x5
# CHECK: st4.8h { v7, v8, v9, v10 }, [x4], x6
# CHECK: st4.2s { v12, v13, v14, v15 }, [x0], x7
# CHECK: st4.4s { v10, v11, v12, v13 }, [x0], x8
# CHECK: st4.2d { v15, v16, v17, v18 }, [x2], x10
0x61 0x28 0x60 0x0d
0x82 0xa4 0x60 0x4d
0xc3 0x70 0x60 0x0d
0xe4 0xb0 0x60 0x4d
# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3]
# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4]
# CHECK: ld4.h { v3, v4, v5, v6 }[2], [x6]
# CHECK: ld4.s { v4, v5, v6, v7 }[3], [x7]
0x61 0x28 0x20 0x0d
0x82 0xa4 0x20 0x4d
0xc3 0x70 0x20 0x0d
0xe4 0xb0 0x20 0x4d
# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3]
# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4]
# CHECK: st4.h { v3, v4, v5, v6 }[2], [x6]
# CHECK: st4.s { v4, v5, v6, v7 }[3], [x7]
0x21 0xe0 0x60 0x0d
0x21 0xe0 0xe2 0x0d
0x21 0xe0 0x60 0x4d
0x21 0xe0 0xe2 0x4d
0x21 0xe4 0x60 0x0d
0x21 0xe4 0xe2 0x0d
0x21 0xe4 0x60 0x4d
0x21 0xe4 0xe2 0x4d
0x21 0xe8 0x60 0x0d
0x21 0xe8 0xe2 0x0d
0x21 0xec 0x60 0x4d
0x21 0xec 0xe2 0x4d
0x21 0xec 0x60 0x0d
0x21 0xec 0xe2 0x0d
# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1]
# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], x2
# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1]
# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], x2
# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1]
# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], x2
# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1]
# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], x2
# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1]
# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], x2
# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1]
# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], x2
# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1]
# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], x2
0x21 0xe0 0xff 0x0d
0x21 0xe0 0xff 0x4d
0x21 0xe4 0xff 0x0d
0x21 0xe4 0xff 0x4d
0x21 0xe8 0xff 0x0d
0x21 0xec 0xff 0x4d
0x21 0xec 0xff 0x0d
# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], #4
# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], #4
# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], #8
# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], #8
# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], #16
# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], #32
# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], #32
0x20 0xe4 0x00 0x2f
0x20 0xe4 0x00 0x6f
0x20 0xe4 0x00 0x0f
0x20 0xe4 0x00 0x4f
# CHECK: movi d0, #0x000000000000ff
# CHECK: movi.2d v0, #0x000000000000ff
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: movi.8b v0, #0x1
# CHECK: movi.16b v0, #0x1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x04 0x00 0x0f
0x20 0x24 0x00 0x0f
0x20 0x44 0x00 0x0f
0x20 0x64 0x00 0x0f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: movi.2s v0, #0x1
# CHECK: movi.2s v0, #0x1, lsl #8
# CHECK: movi.2s v0, #0x1, lsl #16
# CHECK: movi.2s v0, #0x1, lsl #24
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x04 0x00 0x4f
0x20 0x24 0x00 0x4f
0x20 0x44 0x00 0x4f
0x20 0x64 0x00 0x4f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: movi.4s v0, #0x1
# CHECK: movi.4s v0, #0x1, lsl #8
# CHECK: movi.4s v0, #0x1, lsl #16
# CHECK: movi.4s v0, #0x1, lsl #24
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x84 0x00 0x0f
0x20 0xa4 0x00 0x0f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: movi.4h v0, #0x1
# CHECK: movi.4h v0, #0x1, lsl #8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x84 0x00 0x4f
0x20 0xa4 0x00 0x4f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: movi.8h v0, #0x1
# CHECK: movi.8h v0, #0x1, lsl #8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x04 0x00 0x2f
0x20 0x24 0x00 0x2f
0x20 0x44 0x00 0x2f
0x20 0x64 0x00 0x2f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: mvni.2s v0, #0x1
# CHECK: mvni.2s v0, #0x1, lsl #8
# CHECK: mvni.2s v0, #0x1, lsl #16
# CHECK: mvni.2s v0, #0x1, lsl #24
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x04 0x00 0x6f
0x20 0x24 0x00 0x6f
0x20 0x44 0x00 0x6f
0x20 0x64 0x00 0x6f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: mvni.4s v0, #0x1
# CHECK: mvni.4s v0, #0x1, lsl #8
# CHECK: mvni.4s v0, #0x1, lsl #16
# CHECK: mvni.4s v0, #0x1, lsl #24
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x84 0x00 0x2f
0x20 0xa4 0x00 0x2f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: mvni.4h v0, #0x1
# CHECK: mvni.4h v0, #0x1, lsl #8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0x84 0x00 0x6f
0x20 0xa4 0x00 0x6f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: mvni.8h v0, #0x1
# CHECK: mvni.8h v0, #0x1, lsl #8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x20 0xc4 0x00 0x2f
0x20 0xd4 0x00 0x2f
0x20 0xc4 0x00 0x6f
0x20 0xd4 0x00 0x6f
ARM64: hexify printing various immediate operands This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
# CHECK: mvni.2s v0, #0x1, msl #8
# CHECK: mvni.2s v0, #0x1, msl #16
# CHECK: mvni.4s v0, #0x1, msl #8
# CHECK: mvni.4s v0, #0x1, msl #16
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
0x00 0x88 0x21 0x2e
0x00 0x98 0x21 0x2e
0x00 0x98 0xa1 0x2e
0x00 0x98 0x21 0x0e
0x00 0x88 0x21 0x0e
0x00 0x88 0xa1 0x0e
0x00 0x98 0xa1 0x0e
# CHECK: frinta.2s v0, v0
# CHECK: frintx.2s v0, v0
# CHECK: frinti.2s v0, v0
# CHECK: frintm.2s v0, v0
# CHECK: frintn.2s v0, v0
# CHECK: frintp.2s v0, v0
# CHECK: frintz.2s v0, v0
#===-------------------------------------------------------------------------===
# AdvSIMD scalar x index instructions
#===-------------------------------------------------------------------------===
0x00 0x18 0xa0 0x5f
0x00 0x18 0xc0 0x5f
0x00 0x58 0xa0 0x5f
0x00 0x58 0xc0 0x5f
0x00 0x98 0xa0 0x7f
0x00 0x98 0xc0 0x7f
0x00 0x98 0xa0 0x5f
0x00 0x98 0xc0 0x5f
0x00 0x38 0x70 0x5f
0x00 0x38 0xa0 0x5f
0x00 0x78 0x70 0x5f
0x00 0xc8 0x70 0x5f
0x00 0xc8 0xa0 0x5f
0x00 0xb8 0x70 0x5f
0x00 0xb8 0xa0 0x5f
0x00 0xd8 0x70 0x5f
0x00 0xd8 0xa0 0x5f
# CHECK: fmla.s s0, s0, v0[3]
# CHECK: fmla.d d0, d0, v0[1]
# CHECK: fmls.s s0, s0, v0[3]
# CHECK: fmls.d d0, d0, v0[1]
# CHECK: fmulx.s s0, s0, v0[3]
# CHECK: fmulx.d d0, d0, v0[1]
# CHECK: fmul.s s0, s0, v0[3]
# CHECK: fmul.d d0, d0, v0[1]
# CHECK: sqdmlal.h s0, h0, v0[7]
# CHECK: sqdmlal.s d0, s0, v0[3]
# CHECK: sqdmlsl.h s0, h0, v0[7]
# CHECK: sqdmulh.h h0, h0, v0[7]
# CHECK: sqdmulh.s s0, s0, v0[3]
# CHECK: sqdmull.h s0, h0, v0[7]
# CHECK: sqdmull.s d0, s0, v0[3]
# CHECK: sqrdmulh.h h0, h0, v0[7]
# CHECK: sqrdmulh.s s0, s0, v0[3]
#===-------------------------------------------------------------------------===
# AdvSIMD vector x index instructions
#===-------------------------------------------------------------------------===
0x00 0x10 0x80 0x0f
0x00 0x10 0xa0 0x4f
0x00 0x18 0xc0 0x4f
0x00 0x50 0x80 0x0f
0x00 0x50 0xa0 0x4f
0x00 0x58 0xc0 0x4f
0x00 0x90 0x80 0x2f
0x00 0x90 0xa0 0x6f
0x00 0x98 0xc0 0x6f
0x00 0x90 0x80 0x0f
0x00 0x90 0xa0 0x4f
0x00 0x98 0xc0 0x4f
0x00 0x00 0x40 0x2f
0x00 0x00 0x50 0x6f
0x00 0x08 0x80 0x2f
0x00 0x08 0xa0 0x6f
0x00 0x40 0x40 0x2f
0x00 0x40 0x50 0x6f
0x00 0x48 0x80 0x2f
0x00 0x48 0xa0 0x6f
0x00 0x80 0x40 0x0f
0x00 0x80 0x50 0x4f
0x00 0x88 0x80 0x0f
0x00 0x88 0xa0 0x4f
0x00 0x20 0x40 0x0f
0x00 0x20 0x50 0x4f
0x00 0x28 0x80 0x0f
0x00 0x28 0xa0 0x4f
0x00 0x60 0x40 0x0f
0x00 0x60 0x50 0x4f
0x00 0x68 0x80 0x0f
0x00 0x68 0xa0 0x4f
0x00 0xa0 0x40 0x0f
0x00 0xa0 0x50 0x4f
0x00 0xa8 0x80 0x0f
0x00 0xa8 0xa0 0x4f
0x00 0x30 0x40 0x0f
0x00 0x30 0x50 0x4f
0x00 0x38 0x80 0x0f
0x00 0x38 0xa0 0x4f
0x00 0x70 0x40 0x0f
0x00 0x70 0x50 0x4f
0x00 0x78 0x80 0x0f
0x00 0x78 0xa0 0x4f
0x00 0xc0 0x40 0x0f
0x00 0xc0 0x50 0x4f
0x00 0xc8 0x80 0x0f
0x00 0xc8 0xa0 0x4f
0x00 0xb0 0x40 0x0f
0x00 0xb0 0x50 0x4f
0x00 0xb8 0x80 0x0f
0x00 0xb8 0xa0 0x4f
0x00 0xd0 0x40 0x0f
0x00 0xd0 0x50 0x4f
0x00 0xd8 0x80 0x0f
0x00 0xd8 0xa0 0x4f
0x00 0x20 0x40 0x2f
0x00 0x20 0x50 0x6f
0x00 0x28 0x80 0x2f
0x00 0x28 0xa0 0x6f
0x00 0x60 0x40 0x2f
0x00 0x60 0x50 0x6f
0x00 0x68 0x80 0x2f
0x00 0x68 0xa0 0x6f
0x00 0xa0 0x40 0x2f
0x00 0xa0 0x50 0x6f
0x00 0xa8 0x80 0x2f
0x00 0xa8 0xa0 0x6f
# CHECK: fmla.2s v0, v0, v0[0]
# CHECK: fmla.4s v0, v0, v0[1]
# CHECK: fmla.2d v0, v0, v0[1]
# CHECK: fmls.2s v0, v0, v0[0]
# CHECK: fmls.4s v0, v0, v0[1]
# CHECK: fmls.2d v0, v0, v0[1]
# CHECK: fmulx.2s v0, v0, v0[0]
# CHECK: fmulx.4s v0, v0, v0[1]
# CHECK: fmulx.2d v0, v0, v0[1]
# CHECK: fmul.2s v0, v0, v0[0]
# CHECK: fmul.4s v0, v0, v0[1]
# CHECK: fmul.2d v0, v0, v0[1]
# CHECK: mla.4h v0, v0, v0[0]
# CHECK: mla.8h v0, v0, v0[1]
# CHECK: mla.2s v0, v0, v0[2]
# CHECK: mla.4s v0, v0, v0[3]
# CHECK: mls.4h v0, v0, v0[0]
# CHECK: mls.8h v0, v0, v0[1]
# CHECK: mls.2s v0, v0, v0[2]
# CHECK: mls.4s v0, v0, v0[3]
# CHECK: mul.4h v0, v0, v0[0]
# CHECK: mul.8h v0, v0, v0[1]
# CHECK: mul.2s v0, v0, v0[2]
# CHECK: mul.4s v0, v0, v0[3]
# CHECK: smlal.4s v0, v0, v0[0]
# CHECK: smlal2.4s v0, v0, v0[1]
# CHECK: smlal.2d v0, v0, v0[2]
# CHECK: smlal2.2d v0, v0, v0[3]
# CHECK: smlsl.4s v0, v0, v0[0]
# CHECK: smlsl2.4s v0, v0, v0[1]
# CHECK: smlsl.2d v0, v0, v0[2]
# CHECK: smlsl2.2d v0, v0, v0[3]
# CHECK: smull.4s v0, v0, v0[0]
# CHECK: smull2.4s v0, v0, v0[1]
# CHECK: smull.2d v0, v0, v0[2]
# CHECK: smull2.2d v0, v0, v0[3]
# CHECK: sqdmlal.4s v0, v0, v0[0]
# CHECK: sqdmlal2.4s v0, v0, v0[1]
# CHECK: sqdmlal.2d v0, v0, v0[2]
# CHECK: sqdmlal2.2d v0, v0, v0[3]
# CHECK: sqdmlsl.4s v0, v0, v0[0]
# CHECK: sqdmlsl2.4s v0, v0, v0[1]
# CHECK: sqdmlsl.2d v0, v0, v0[2]
# CHECK: sqdmlsl2.2d v0, v0, v0[3]
# CHECK: sqdmulh.4h v0, v0, v0[0]
# CHECK: sqdmulh.8h v0, v0, v0[1]
# CHECK: sqdmulh.2s v0, v0, v0[2]
# CHECK: sqdmulh.4s v0, v0, v0[3]
# CHECK: sqdmull.4s v0, v0, v0[0]
# CHECK: sqdmull2.4s v0, v0, v0[1]
# CHECK: sqdmull.2d v0, v0, v0[2]
# CHECK: sqdmull2.2d v0, v0, v0[3]
# CHECK: sqrdmulh.4h v0, v0, v0[0]
# CHECK: sqrdmulh.8h v0, v0, v0[1]
# CHECK: sqrdmulh.2s v0, v0, v0[2]
# CHECK: sqrdmulh.4s v0, v0, v0[3]
# CHECK: umlal.4s v0, v0, v0[0]
# CHECK: umlal2.4s v0, v0, v0[1]
# CHECK: umlal.2d v0, v0, v0[2]
# CHECK: umlal2.2d v0, v0, v0[3]
# CHECK: umlsl.4s v0, v0, v0[0]
# CHECK: umlsl2.4s v0, v0, v0[1]
# CHECK: umlsl.2d v0, v0, v0[2]
# CHECK: umlsl2.2d v0, v0, v0[3]
# CHECK: umull.4s v0, v0, v0[0]
# CHECK: umull2.4s v0, v0, v0[1]
# CHECK: umull.2d v0, v0, v0[2]
# CHECK: umull2.2d v0, v0, v0[3]
#===-------------------------------------------------------------------------===
# AdvSIMD scalar + shift instructions
#===-------------------------------------------------------------------------===
0x00 0x54 0x41 0x5f
0x00 0x54 0x41 0x7f
0x00 0x9c 0x09 0x5f
0x00 0x9c 0x12 0x5f
0x00 0x9c 0x23 0x5f
0x00 0x8c 0x09 0x7f
0x00 0x8c 0x12 0x7f
0x00 0x8c 0x23 0x7f
0x00 0x64 0x09 0x7f
0x00 0x64 0x12 0x7f
0x00 0x64 0x23 0x7f
0x00 0x64 0x44 0x7f
0x00 0x74 0x09 0x5f
0x00 0x74 0x12 0x5f
0x00 0x74 0x23 0x5f
0x00 0x74 0x44 0x5f
0x00 0x94 0x09 0x5f
0x00 0x94 0x12 0x5f
0x00 0x94 0x23 0x5f
0x00 0x84 0x09 0x7f
0x00 0x84 0x12 0x7f
0x00 0x84 0x23 0x7f
0x00 0x44 0x41 0x7f
0x00 0x24 0x41 0x5f
0x00 0x34 0x41 0x5f
0x00 0x04 0x41 0x5f
0x00 0xe4 0x21 0x7f
0x00 0xe4 0x42 0x7f
0x00 0x9c 0x09 0x7f
0x00 0x9c 0x12 0x7f
0x00 0x9c 0x23 0x7f
0x00 0x74 0x09 0x7f
0x00 0x74 0x12 0x7f
0x00 0x74 0x23 0x7f
0x00 0x74 0x44 0x7f
0x00 0x94 0x09 0x7f
0x00 0x94 0x12 0x7f
0x00 0x94 0x23 0x7f
0x00 0x24 0x41 0x7f
0x00 0x34 0x41 0x7f
0x00 0x04 0x41 0x7f
0x00 0x14 0x41 0x7f
# CHECK: shl d0, d0, #1
# CHECK: sli d0, d0, #1
# CHECK: sqrshrn b0, h0, #7
# CHECK: sqrshrn h0, s0, #14
# CHECK: sqrshrn s0, d0, #29
# CHECK: sqrshrun b0, h0, #7
# CHECK: sqrshrun h0, s0, #14
# CHECK: sqrshrun s0, d0, #29
# CHECK: sqshlu b0, b0, #1
# CHECK: sqshlu h0, h0, #2
# CHECK: sqshlu s0, s0, #3
# CHECK: sqshlu d0, d0, #4
# CHECK: sqshl b0, b0, #1
# CHECK: sqshl h0, h0, #2
# CHECK: sqshl s0, s0, #3
# CHECK: sqshl d0, d0, #4
# CHECK: sqshrn b0, h0, #7
# CHECK: sqshrn h0, s0, #14
# CHECK: sqshrn s0, d0, #29
# CHECK: sqshrun b0, h0, #7
# CHECK: sqshrun h0, s0, #14
# CHECK: sqshrun s0, d0, #29
# CHECK: sri d0, d0, #63
# CHECK: srshr d0, d0, #63
# CHECK: srsra d0, d0, #63
# CHECK: sshr d0, d0, #63
# CHECK: ucvtf s0, s0, #31
# CHECK: ucvtf d0, d0, #62
# CHECK: uqrshrn b0, h0, #7
# CHECK: uqrshrn h0, s0, #14
# CHECK: uqrshrn s0, d0, #29
# CHECK: uqshl b0, b0, #1
# CHECK: uqshl h0, h0, #2
# CHECK: uqshl s0, s0, #3
# CHECK: uqshl d0, d0, #4
# CHECK: uqshrn b0, h0, #7
# CHECK: uqshrn h0, s0, #14
# CHECK: uqshrn s0, d0, #29
# CHECK: urshr d0, d0, #63
# CHECK: ursra d0, d0, #63
# CHECK: ushr d0, d0, #63
# CHECK: usra d0, d0, #63
#===-------------------------------------------------------------------------===
# AdvSIMD vector + shift instructions
#===-------------------------------------------------------------------------===
0x00 0xfc 0x21 0x0f
0x00 0xfc 0x22 0x4f
0x00 0xfc 0x43 0x4f
0x00 0xfc 0x21 0x2f
0x00 0xfc 0x22 0x6f
0x00 0xfc 0x43 0x6f
0x00 0x8c 0x09 0x0f
0x00 0x8c 0x0a 0x4f
0x00 0x8c 0x13 0x0f
0x00 0x8c 0x14 0x4f
0x00 0x8c 0x25 0x0f
0x00 0x8c 0x26 0x4f
0x00 0xe4 0x21 0x0f
0x00 0xe4 0x22 0x4f
0x00 0xe4 0x43 0x4f
0x00 0x54 0x09 0x0f
0x00 0x54 0x0a 0x4f
0x00 0x54 0x13 0x0f
0x00 0x54 0x14 0x4f
0x00 0x54 0x25 0x0f
0x00 0x54 0x26 0x4f
0x00 0x54 0x47 0x4f
0x00 0x84 0x09 0x0f
0x00 0x84 0x0a 0x4f
0x00 0x84 0x13 0x0f
0x00 0x84 0x14 0x4f
0x00 0x84 0x25 0x0f
0x00 0x84 0x26 0x4f
0x00 0x54 0x09 0x2f
0x00 0x54 0x0a 0x6f
0x00 0x54 0x13 0x2f
0x00 0x54 0x14 0x6f
0x00 0x54 0x25 0x2f
0x00 0x54 0x26 0x6f
0x00 0x54 0x47 0x6f
0x00 0x9c 0x09 0x0f
0x00 0x9c 0x0a 0x4f
0x00 0x9c 0x13 0x0f
0x00 0x9c 0x14 0x4f
0x00 0x9c 0x25 0x0f
0x00 0x9c 0x26 0x4f
0x00 0x8c 0x09 0x2f
0x00 0x8c 0x0a 0x6f
0x00 0x8c 0x13 0x2f
0x00 0x8c 0x14 0x6f
0x00 0x8c 0x25 0x2f
0x00 0x8c 0x26 0x6f
0x00 0x64 0x09 0x2f
0x00 0x64 0x0a 0x6f
0x00 0x64 0x13 0x2f
0x00 0x64 0x14 0x6f
0x00 0x64 0x25 0x2f
0x00 0x64 0x26 0x6f
0x00 0x64 0x47 0x6f
0x00 0x74 0x09 0x0f
0x00 0x74 0x0a 0x4f
0x00 0x74 0x13 0x0f
0x00 0x74 0x14 0x4f
0x00 0x74 0x25 0x0f
0x00 0x74 0x26 0x4f
0x00 0x74 0x47 0x4f
0x00 0x94 0x09 0x0f
0x00 0x94 0x0a 0x4f
0x00 0x94 0x13 0x0f
0x00 0x94 0x14 0x4f
0x00 0x94 0x25 0x0f
0x00 0x94 0x26 0x4f
0x00 0x84 0x09 0x2f
0x00 0x84 0x0a 0x6f
0x00 0x84 0x13 0x2f
0x00 0x84 0x14 0x6f
0x00 0x84 0x25 0x2f
0x00 0x84 0x26 0x6f
0x00 0x44 0x09 0x2f
0x00 0x44 0x0a 0x6f
0x00 0x44 0x13 0x2f
0x00 0x44 0x14 0x6f
0x00 0x44 0x25 0x2f
0x00 0x44 0x26 0x6f
0x00 0x44 0x47 0x6f
0x00 0x24 0x09 0x0f
0x00 0x24 0x0a 0x4f
0x00 0x24 0x13 0x0f
0x00 0x24 0x14 0x4f
0x00 0x24 0x25 0x0f
0x00 0x24 0x26 0x4f
0x00 0x24 0x47 0x4f
0x00 0x34 0x09 0x0f
0x00 0x34 0x0a 0x4f
0x00 0x34 0x13 0x0f
0x00 0x34 0x14 0x4f
0x00 0x34 0x25 0x0f
0x00 0x34 0x26 0x4f
0x00 0x34 0x47 0x4f
0x00 0xa4 0x09 0x0f
0x00 0xa4 0x0a 0x4f
0x00 0xa4 0x13 0x0f
0x00 0xa4 0x14 0x4f
0x00 0xa4 0x25 0x0f
0x00 0xa4 0x26 0x4f
0x00 0x04 0x09 0x0f
0x00 0x04 0x0a 0x4f
0x00 0x04 0x13 0x0f
0x00 0x04 0x14 0x4f
0x00 0x04 0x25 0x0f
0x00 0x04 0x26 0x4f
0x00 0x04 0x47 0x4f
0x00 0x04 0x09 0x0f
0x00 0x14 0x0a 0x4f
0x00 0x14 0x13 0x0f
0x00 0x14 0x14 0x4f
0x00 0x14 0x25 0x0f
0x00 0x14 0x26 0x4f
0x00 0x14 0x47 0x4f
0x00 0x14 0x40 0x5f
0x00 0xe4 0x21 0x2f
0x00 0xe4 0x22 0x6f
0x00 0xe4 0x43 0x6f
0x00 0x9c 0x09 0x2f
0x00 0x9c 0x0a 0x6f
0x00 0x9c 0x13 0x2f
0x00 0x9c 0x14 0x6f
0x00 0x9c 0x25 0x2f
0x00 0x9c 0x26 0x6f
0x00 0x74 0x09 0x2f
0x00 0x74 0x0a 0x6f
0x00 0x74 0x13 0x2f
0x00 0x74 0x14 0x6f
0x00 0x74 0x25 0x2f
0x00 0x74 0x26 0x6f
0x00 0x74 0x47 0x6f
0x00 0x94 0x09 0x2f
0x00 0x94 0x0a 0x6f
0x00 0x94 0x13 0x2f
0x00 0x94 0x14 0x6f
0x00 0x94 0x25 0x2f
0x00 0x94 0x26 0x6f
0x00 0x24 0x09 0x2f
0x00 0x24 0x0a 0x6f
0x00 0x24 0x13 0x2f
0x00 0x24 0x14 0x6f
0x00 0x24 0x25 0x2f
0x00 0x24 0x26 0x6f
0x00 0x24 0x47 0x6f
0x00 0x34 0x09 0x2f
0x00 0x34 0x0a 0x6f
0x00 0x34 0x13 0x2f
0x00 0x34 0x14 0x6f
0x00 0x34 0x25 0x2f
0x00 0x34 0x26 0x6f
0x00 0x34 0x47 0x6f
0x00 0xa4 0x09 0x2f
0x00 0xa4 0x0a 0x6f
0x00 0xa4 0x13 0x2f
0x00 0xa4 0x14 0x6f
0x00 0xa4 0x25 0x2f
0x00 0xa4 0x26 0x6f
0x00 0x04 0x09 0x2f
0x00 0x04 0x0a 0x6f
0x00 0x04 0x13 0x2f
0x00 0x04 0x14 0x6f
0x00 0x04 0x25 0x2f
0x00 0x04 0x26 0x6f
0x00 0x04 0x47 0x6f
0x00 0x14 0x09 0x2f
0x00 0x14 0x0a 0x6f
0x00 0x14 0x13 0x2f
0x00 0x14 0x14 0x6f
0x00 0x14 0x25 0x2f
0x00 0x14 0x26 0x6f
0x00 0x14 0x47 0x6f
# CHECK: fcvtzs.2s v0, v0, #31
# CHECK: fcvtzs.4s v0, v0, #30
# CHECK: fcvtzs.2d v0, v0, #61
# CHECK: fcvtzu.2s v0, v0, #31
# CHECK: fcvtzu.4s v0, v0, #30
# CHECK: fcvtzu.2d v0, v0, #61
# CHECK: rshrn.8b v0, v0, #7
# CHECK: rshrn2.16b v0, v0, #6
# CHECK: rshrn.4h v0, v0, #13
# CHECK: rshrn2.8h v0, v0, #12
# CHECK: rshrn.2s v0, v0, #27
# CHECK: rshrn2.4s v0, v0, #26
# CHECK: scvtf.2s v0, v0, #31
# CHECK: scvtf.4s v0, v0, #30
# CHECK: scvtf.2d v0, v0, #61
# CHECK: shl.8b v0, v0, #1
# CHECK: shl.16b v0, v0, #2
# CHECK: shl.4h v0, v0, #3
# CHECK: shl.8h v0, v0, #4
# CHECK: shl.2s v0, v0, #5
# CHECK: shl.4s v0, v0, #6
# CHECK: shl.2d v0, v0, #7
# CHECK: shrn.8b v0, v0, #7
# CHECK: shrn2.16b v0, v0, #6
# CHECK: shrn.4h v0, v0, #13
# CHECK: shrn2.8h v0, v0, #12
# CHECK: shrn.2s v0, v0, #27
# CHECK: shrn2.4s v0, v0, #26
# CHECK: sli.8b v0, v0, #1
# CHECK: sli.16b v0, v0, #2
# CHECK: sli.4h v0, v0, #3
# CHECK: sli.8h v0, v0, #4
# CHECK: sli.2s v0, v0, #5
# CHECK: sli.4s v0, v0, #6
# CHECK: sli.2d v0, v0, #7
# CHECK: sqrshrn.8b v0, v0, #7
# CHECK: sqrshrn2.16b v0, v0, #6
# CHECK: sqrshrn.4h v0, v0, #13
# CHECK: sqrshrn2.8h v0, v0, #12
# CHECK: sqrshrn.2s v0, v0, #27
# CHECK: sqrshrn2.4s v0, v0, #26
# CHECK: sqrshrun.8b v0, v0, #7
# CHECK: sqrshrun2.16b v0, v0, #6
# CHECK: sqrshrun.4h v0, v0, #13
# CHECK: sqrshrun2.8h v0, v0, #12
# CHECK: sqrshrun.2s v0, v0, #27
# CHECK: sqrshrun2.4s v0, v0, #26
# CHECK: sqshlu.8b v0, v0, #1
# CHECK: sqshlu.16b v0, v0, #2
# CHECK: sqshlu.4h v0, v0, #3
# CHECK: sqshlu.8h v0, v0, #4
# CHECK: sqshlu.2s v0, v0, #5
# CHECK: sqshlu.4s v0, v0, #6
# CHECK: sqshlu.2d v0, v0, #7
# CHECK: sqshl.8b v0, v0, #1
# CHECK: sqshl.16b v0, v0, #2
# CHECK: sqshl.4h v0, v0, #3
# CHECK: sqshl.8h v0, v0, #4
# CHECK: sqshl.2s v0, v0, #5
# CHECK: sqshl.4s v0, v0, #6
# CHECK: sqshl.2d v0, v0, #7
# CHECK: sqshrn.8b v0, v0, #7
# CHECK: sqshrn2.16b v0, v0, #6
# CHECK: sqshrn.4h v0, v0, #13
# CHECK: sqshrn2.8h v0, v0, #12
# CHECK: sqshrn.2s v0, v0, #27
# CHECK: sqshrn2.4s v0, v0, #26
# CHECK: sqshrun.8b v0, v0, #7
# CHECK: sqshrun2.16b v0, v0, #6
# CHECK: sqshrun.4h v0, v0, #13
# CHECK: sqshrun2.8h v0, v0, #12
# CHECK: sqshrun.2s v0, v0, #27
# CHECK: sqshrun2.4s v0, v0, #26
# CHECK: sri.8b v0, v0, #7
# CHECK: sri.16b v0, v0, #6
# CHECK: sri.4h v0, v0, #13
# CHECK: sri.8h v0, v0, #12
# CHECK: sri.2s v0, v0, #27
# CHECK: sri.4s v0, v0, #26
# CHECK: sri.2d v0, v0, #57
# CHECK: srshr.8b v0, v0, #7
# CHECK: srshr.16b v0, v0, #6
# CHECK: srshr.4h v0, v0, #13
# CHECK: srshr.8h v0, v0, #12
# CHECK: srshr.2s v0, v0, #27
# CHECK: srshr.4s v0, v0, #26
# CHECK: srshr.2d v0, v0, #57
# CHECK: srsra.8b v0, v0, #7
# CHECK: srsra.16b v0, v0, #6
# CHECK: srsra.4h v0, v0, #13
# CHECK: srsra.8h v0, v0, #12
# CHECK: srsra.2s v0, v0, #27
# CHECK: srsra.4s v0, v0, #26
# CHECK: srsra.2d v0, v0, #57
# CHECK: sshll.8h v0, v0, #1
# CHECK: sshll2.8h v0, v0, #2
# CHECK: sshll.4s v0, v0, #3
# CHECK: sshll2.4s v0, v0, #4
# CHECK: sshll.2d v0, v0, #5
# CHECK: sshll2.2d v0, v0, #6
# CHECK: sshr.8b v0, v0, #7
# CHECK: sshr.16b v0, v0, #6
# CHECK: sshr.4h v0, v0, #13
# CHECK: sshr.8h v0, v0, #12
# CHECK: sshr.2s v0, v0, #27
# CHECK: sshr.4s v0, v0, #26
# CHECK: sshr.2d v0, v0, #57
# CHECK: sshr.8b v0, v0, #7
# CHECK: ssra.16b v0, v0, #6
# CHECK: ssra.4h v0, v0, #13
# CHECK: ssra.8h v0, v0, #12
# CHECK: ssra.2s v0, v0, #27
# CHECK: ssra.4s v0, v0, #26
# CHECK: ssra.2d v0, v0, #57
# CHECK: ssra d0, d0, #64
# CHECK: ucvtf.2s v0, v0, #31
# CHECK: ucvtf.4s v0, v0, #30
# CHECK: ucvtf.2d v0, v0, #61
# CHECK: uqrshrn.8b v0, v0, #7
# CHECK: uqrshrn2.16b v0, v0, #6
# CHECK: uqrshrn.4h v0, v0, #13
# CHECK: uqrshrn2.8h v0, v0, #12
# CHECK: uqrshrn.2s v0, v0, #27
# CHECK: uqrshrn2.4s v0, v0, #26
# CHECK: uqshl.8b v0, v0, #1
# CHECK: uqshl.16b v0, v0, #2
# CHECK: uqshl.4h v0, v0, #3
# CHECK: uqshl.8h v0, v0, #4
# CHECK: uqshl.2s v0, v0, #5
# CHECK: uqshl.4s v0, v0, #6
# CHECK: uqshl.2d v0, v0, #7
# CHECK: uqshrn.8b v0, v0, #7
# CHECK: uqshrn2.16b v0, v0, #6
# CHECK: uqshrn.4h v0, v0, #13
# CHECK: uqshrn2.8h v0, v0, #12
# CHECK: uqshrn.2s v0, v0, #27
# CHECK: uqshrn2.4s v0, v0, #26
# CHECK: urshr.8b v0, v0, #7
# CHECK: urshr.16b v0, v0, #6
# CHECK: urshr.4h v0, v0, #13
# CHECK: urshr.8h v0, v0, #12
# CHECK: urshr.2s v0, v0, #27
# CHECK: urshr.4s v0, v0, #26
# CHECK: urshr.2d v0, v0, #57
# CHECK: ursra.8b v0, v0, #7
# CHECK: ursra.16b v0, v0, #6
# CHECK: ursra.4h v0, v0, #13
# CHECK: ursra.8h v0, v0, #12
# CHECK: ursra.2s v0, v0, #27
# CHECK: ursra.4s v0, v0, #26
# CHECK: ursra.2d v0, v0, #57
# CHECK: ushll.8h v0, v0, #1
# CHECK: ushll2.8h v0, v0, #2
# CHECK: ushll.4s v0, v0, #3
# CHECK: ushll2.4s v0, v0, #4
# CHECK: ushll.2d v0, v0, #5
# CHECK: ushll2.2d v0, v0, #6
# CHECK: ushr.8b v0, v0, #7
# CHECK: ushr.16b v0, v0, #6
# CHECK: ushr.4h v0, v0, #13
# CHECK: ushr.8h v0, v0, #12
# CHECK: ushr.2s v0, v0, #27
# CHECK: ushr.4s v0, v0, #26
# CHECK: ushr.2d v0, v0, #57
# CHECK: usra.8b v0, v0, #7
# CHECK: usra.16b v0, v0, #6
# CHECK: usra.4h v0, v0, #13
# CHECK: usra.8h v0, v0, #12
# CHECK: usra.2s v0, v0, #27
# CHECK: usra.4s v0, v0, #26
# CHECK: usra.2d v0, v0, #57
0x00 0xe0 0x20 0x0e
0x00 0xe0 0x20 0x4e
0x00 0xe0 0xe0 0x0e
0x00 0xe0 0xe0 0x4e
# CHECK: pmull.8h v0, v0, v0
# CHECK: pmull2.8h v0, v0, v0
# CHECK: pmull.1q v0, v0, v0
# CHECK: pmull2.1q v0, v0, v0
0x41 0xd8 0x70 0x7e
0x83 0xd8 0x30 0x7e
# CHECK: faddp.2d d1, v2
# CHECK: faddp.2s s3, v4
0x82 0x60 0x01 0x4e
0x80 0x60 0x01 0x0e
0xa2 0x00 0x01 0x4e
0xa0 0x00 0x01 0x0e
0xa2 0x40 0x01 0x4e
0xa0 0x40 0x01 0x0e
0xc2 0x20 0x01 0x4e
0xc0 0x20 0x01 0x0e
# CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1
# CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1
# CHECK: tbl.16b v2, { v5 }, v1
# CHECK: tbl.8b v0, { v5 }, v1
# CHECK: tbl.16b v2, { v5, v6, v7 }, v1
# CHECK: tbl.8b v0, { v5, v6, v7 }, v1
# CHECK: tbl.16b v2, { v6, v7 }, v1
# CHECK: tbl.8b v0, { v6, v7 }, v1
#
0x82 0x70 0x01 0x4e
0x80 0x70 0x01 0x0e
0xa2 0x10 0x01 0x4e
0xa0 0x10 0x01 0x0e
0xa2 0x50 0x01 0x4e
0xa0 0x50 0x01 0x0e
0xc2 0x30 0x01 0x4e
0xc0 0x30 0x01 0x0e
# CHECK: tbx.16b v2, { v4, v5, v6, v7 }, v1
# CHECK: tbx.8b v0, { v4, v5, v6, v7 }, v1
# CHECK: tbx.16b v2, { v5 }, v1
# CHECK: tbx.8b v0, { v5 }, v1
# CHECK: tbx.16b v2, { v5, v6, v7 }, v1
# CHECK: tbx.8b v0, { v5, v6, v7 }, v1
# CHECK: tbx.16b v2, { v6, v7 }, v1
# CHECK: tbx.8b v0, { v6, v7 }, v1
#
0x00 0x80 0x20 0x0e
0x00 0x80 0x20 0x4e
0x00 0x80 0xa0 0x0e
0x00 0x80 0xa0 0x4e
# CHECK: smlal.8h v0, v0, v0
# CHECK: smlal2.8h v0, v0, v0
# CHECK: smlal.2d v0, v0, v0
# CHECK: smlal2.2d v0, v0, v0
0x00 0x80 0x20 0x2e
0x00 0x80 0x20 0x6e
0x00 0x80 0xa0 0x2e
0x00 0x80 0xa0 0x6e
# CHECK: umlal.8h v0, v0, v0
# CHECK: umlal2.8h v0, v0, v0
# CHECK: umlal.2d v0, v0, v0
# CHECK: umlal2.2d v0, v0, v0
0x00 0x90 0x60 0x5e
0x00 0x90 0xa0 0x5e
0x00 0xb0 0x60 0x5e
0x00 0xb0 0xa0 0x5e
# CHECK: sqdmlal s0, h0, h0
# CHECK: sqdmlal d0, s0, s0
# CHECK: sqdmlsl s0, h0, h0
# CHECK: sqdmlsl d0, s0, s0
0xaa 0xc5 0xc7 0x4d
0xaa 0xc9 0xc7 0x4d
0xaa 0xc1 0xc7 0x4d
# CHECK: ld1r.8h { v10 }, [x13], x7
# CHECK: ld1r.4s { v10 }, [x13], x7
# CHECK: ld1r.16b { v10 }, [x13], x7
0x00 0xd0 0x60 0x5e
0x00 0xd0 0xa0 0x5e
# CHECK: sqdmull s0, h0, h0
# CHECK: sqdmull d0, s0, s0
0x00 0xd8 0xa1 0x7e
0x00 0xd8 0xe1 0x7e
# CHECK: frsqrte s0, s0
# CHECK: frsqrte d0, d0
0xca 0xcd 0xc7 0x4d
0xea 0xc9 0xe7 0x4d
0xea 0xe9 0xc7 0x4d
0xea 0xe9 0xe7 0x4d
# CHECK: ld1r.2d { v10 }, [x14], x7
# CHECK: ld2r.4s { v10, v11 }, [x15], x7
# CHECK: ld3r.4s { v10, v11, v12 }, [x15], x7
# CHECK: ld4r.4s { v10, v11, v12, v13 }, [x15], x7
#===-------------------------------------------------------------------------===
# AdvSIMD scalar three same
#===-------------------------------------------------------------------------===
0x62 0xdc 0x21 0x5e
# CHECK: fmulx s2, s3, s1
0x62 0xdc 0x61 0x5e
# CHECK: fmulx d2, d3, d1
# rdar://12511369
0xe8 0x6b 0xdf 0x4c
# CHECK: ld1.4s { v8, v9, v10 }, [sp], #48
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