Peter Collingbourne b28abbf98b ARM: Only enforce 4-byte alignment on Thumb-2 functions with constant pools. ... This appears to have been introduced back in r76698 as part of an unrelated change. I can find no official ARM documentation stating that Thumb-2 functions require 4-byte alignment; in fact, ARM documentation appears to contradict this (see, e.g., ARM Architecture Reference Manual Thumb-2 Supplement, section 2.6.1: "Thumb-2 enforces 16-bit alignment on all instructions."). Also remove code that sets alignment for ARM functions, which is redundant with code in the MachineFunction constructor, and remove the hidden -arm-align-constant-islands flag, which has been enabled by default since r146739 (Dec 2011) and has probably received sufficient testing by now. Differential Revision: http://reviews.llvm.org/D9138 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235636 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-23 20:31:22 +00:00
..
AArch64	[AArch64] LORID_EL1 register must be treated as read-only	2015-04-20 16:54:37 +00:00
ARM	ARM: Only enforce 4-byte alignment on Thumb-2 functions with constant pools.	2015-04-23 20:31:22 +00:00
AsmParser	Add support for .ifnes psuedo-op.	2015-03-18 14:20:54 +00:00
COFF	Add a proper fix for pr23025.	2015-04-17 11:27:13 +00:00
Disassembler	[PowerPC] Enable printing instructions using aliases	2015-04-23 18:30:38 +00:00
ELF	Look past locals in comdats.	2015-04-20 12:44:06 +00:00
Hexagon	Expand MUX instructions early on Hexagon	2015-03-31 13:35:12 +00:00
MachO	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-04-03 01:46:11 +00:00
Markup
Mips	[mips] [IAS] Implement the .asciiz directive.	2015-04-21 11:50:52 +00:00
PowerPC	[PowerPC] Enable printing instructions using aliases	2015-04-23 18:30:38 +00:00
R600	R600/SI: Add missing -mcpu=SI to assembler test	2015-04-23 19:33:55 +00:00
Sparc
SystemZ	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
X86	AVX-512: Added VPMOVx2M instructions for SKX,	2015-04-21 14:38:31 +00:00