2009-11-07 22:00:39 +00:00
|
|
|
//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
|
2009-06-26 21:28:53 +00:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
2009-07-02 22:18:33 +00:00
|
|
|
// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
|
2009-06-26 21:28:53 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2009-11-06 23:52:48 +00:00
|
|
|
#include "Thumb2InstrInfo.h"
|
2009-06-26 21:28:53 +00:00
|
|
|
#include "ARM.h"
|
2009-11-06 23:52:48 +00:00
|
|
|
#include "ARMConstantPoolValue.h"
|
2009-07-28 05:48:47 +00:00
|
|
|
#include "ARMAddressingModes.h"
|
2009-06-26 21:28:53 +00:00
|
|
|
#include "ARMGenInstrInfo.inc"
|
|
|
|
#include "ARMMachineFunctionInfo.h"
|
2010-06-18 23:09:54 +00:00
|
|
|
#include "Thumb2InstrInfo.h"
|
2009-06-26 21:28:53 +00:00
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
|
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
2009-11-01 22:04:35 +00:00
|
|
|
#include "llvm/CodeGen/MachineMemOperand.h"
|
|
|
|
#include "llvm/CodeGen/PseudoSourceValue.h"
|
2009-06-26 21:28:53 +00:00
|
|
|
#include "llvm/ADT/SmallVector.h"
|
2010-06-25 22:42:03 +00:00
|
|
|
#include "llvm/Support/CommandLine.h"
|
2009-06-26 21:28:53 +00:00
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
2010-10-01 20:28:06 +00:00
|
|
|
static cl::opt<bool>
|
|
|
|
OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
|
|
|
|
cl::desc("Use old-style Thumb2 if-conversion heuristics"),
|
|
|
|
cl::init(false));
|
|
|
|
|
2009-11-02 00:10:38 +00:00
|
|
|
Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
|
|
|
|
: ARMBaseInstrInfo(STI), RI(*this, STI) {
|
2009-06-26 21:28:53 +00:00
|
|
|
}
|
|
|
|
|
2009-07-11 06:43:01 +00:00
|
|
|
unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
|
2009-07-08 16:09:28 +00:00
|
|
|
// FIXME
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-18 23:09:54 +00:00
|
|
|
void
|
|
|
|
Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
|
|
|
|
MachineBasicBlock *NewDest) const {
|
|
|
|
MachineBasicBlock *MBB = Tail->getParent();
|
|
|
|
ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
|
|
|
|
if (!AFI->hasITBlocks()) {
|
|
|
|
TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the first instruction of Tail is predicated, we may have to update
|
|
|
|
// the IT instruction.
|
|
|
|
unsigned PredReg = 0;
|
|
|
|
ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
|
|
|
|
MachineBasicBlock::iterator MBBI = Tail;
|
|
|
|
if (CC != ARMCC::AL)
|
|
|
|
// Expecting at least the t2IT instruction before it.
|
|
|
|
--MBBI;
|
|
|
|
|
|
|
|
// Actually replace the tail.
|
|
|
|
TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
|
|
|
|
|
|
|
|
// Fix up IT.
|
|
|
|
if (CC != ARMCC::AL) {
|
|
|
|
MachineBasicBlock::iterator E = MBB->begin();
|
|
|
|
unsigned Count = 4; // At most 4 instructions in an IT block.
|
|
|
|
while (Count && MBBI != E) {
|
|
|
|
if (MBBI->isDebugValue()) {
|
|
|
|
--MBBI;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (MBBI->getOpcode() == ARM::t2IT) {
|
|
|
|
unsigned Mask = MBBI->getOperand(1).getImm();
|
|
|
|
if (Count == 4)
|
|
|
|
MBBI->eraseFromParent();
|
|
|
|
else {
|
|
|
|
unsigned MaskOn = 1 << Count;
|
|
|
|
unsigned MaskOff = ~(MaskOn - 1);
|
|
|
|
MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
--MBBI;
|
|
|
|
--Count;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Ctrl flow can reach here if branch folding is run before IT block
|
|
|
|
// formation pass.
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-06-22 01:18:16 +00:00
|
|
|
bool
|
|
|
|
Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MBBI) const {
|
2011-02-22 07:07:59 +00:00
|
|
|
while (MBBI->isDebugValue()) {
|
2011-02-21 23:40:47 +00:00
|
|
|
++MBBI;
|
2011-02-22 07:07:59 +00:00
|
|
|
if (MBBI == MBB.end())
|
|
|
|
return false;
|
|
|
|
}
|
2011-02-21 23:40:47 +00:00
|
|
|
|
2010-06-22 01:18:16 +00:00
|
|
|
unsigned PredReg = 0;
|
|
|
|
return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
|
2010-06-25 22:42:03 +00:00
|
|
|
}
|
2010-06-22 01:18:16 +00:00
|
|
|
|
2010-07-11 06:33:54 +00:00
|
|
|
void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I, DebugLoc DL,
|
|
|
|
unsigned DestReg, unsigned SrcReg,
|
|
|
|
bool KillSrc) const {
|
2009-07-27 00:33:08 +00:00
|
|
|
// Handle SPR, DPR, and QPR copies.
|
2010-07-11 06:33:54 +00:00
|
|
|
if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
|
|
|
|
return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
|
|
|
|
|
|
|
|
bool tDest = ARM::tGPRRegClass.contains(DestReg);
|
|
|
|
bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
|
|
|
|
unsigned Opc = ARM::tMOVgpr2gpr;
|
|
|
|
if (tDest && tSrc)
|
|
|
|
Opc = ARM::tMOVr;
|
|
|
|
else if (tSrc)
|
|
|
|
Opc = ARM::tMOVtgpr2gpr;
|
|
|
|
else if (tDest)
|
|
|
|
Opc = ARM::tMOVgpr2tgpr;
|
|
|
|
|
|
|
|
BuildMI(MBB, I, DL, get(Opc), DestReg)
|
|
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
2009-07-16 23:26:06 +00:00
|
|
|
}
|
2009-07-27 03:14:20 +00:00
|
|
|
|
|
|
|
void Thumb2InstrInfo::
|
|
|
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
|
|
unsigned SrcReg, bool isKill, int FI,
|
2010-05-06 19:06:44 +00:00
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
const TargetRegisterInfo *TRI) const {
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
|
|
|
|
RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
|
2010-05-06 19:06:44 +00:00
|
|
|
DebugLoc DL;
|
|
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
|
|
|
|
2009-11-01 22:04:35 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
MachineFrameInfo &MFI = *MF.getFrameInfo();
|
|
|
|
MachineMemOperand *MMO =
|
2010-09-21 04:39:43 +00:00
|
|
|
MF.getMachineMemOperand(
|
|
|
|
MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
|
|
|
|
MachineMemOperand::MOStore,
|
2009-11-01 22:04:35 +00:00
|
|
|
MFI.getObjectSize(FI),
|
|
|
|
MFI.getObjectAlignment(FI));
|
2009-07-27 03:14:20 +00:00
|
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
|
|
|
|
.addReg(SrcReg, getKillRegState(isKill))
|
2009-11-01 22:04:35 +00:00
|
|
|
.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
|
2009-07-27 03:14:20 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-05-06 19:06:44 +00:00
|
|
|
ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
|
2009-07-27 03:14:20 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void Thumb2InstrInfo::
|
|
|
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
|
|
unsigned DestReg, int FI,
|
2010-05-06 19:06:44 +00:00
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
const TargetRegisterInfo *TRI) const {
|
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 02:41:01 +00:00
|
|
|
if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
|
|
|
|
RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
|
2010-05-06 19:06:44 +00:00
|
|
|
DebugLoc DL;
|
|
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
|
|
|
|
2009-11-01 22:04:35 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
MachineFrameInfo &MFI = *MF.getFrameInfo();
|
|
|
|
MachineMemOperand *MMO =
|
2010-09-21 04:39:43 +00:00
|
|
|
MF.getMachineMemOperand(
|
|
|
|
MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
|
|
|
|
MachineMemOperand::MOLoad,
|
2009-11-01 22:04:35 +00:00
|
|
|
MFI.getObjectSize(FI),
|
|
|
|
MFI.getObjectAlignment(FI));
|
2009-07-27 03:14:20 +00:00
|
|
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
|
2009-11-01 22:04:35 +00:00
|
|
|
.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
|
2009-07-27 03:14:20 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-05-06 19:06:44 +00:00
|
|
|
ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
|
2009-07-27 03:14:20 +00:00
|
|
|
}
|
2009-07-28 05:48:47 +00:00
|
|
|
|
|
|
|
void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MBBI, DebugLoc dl,
|
|
|
|
unsigned DestReg, unsigned BaseReg, int NumBytes,
|
|
|
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
2011-03-05 18:43:32 +00:00
|
|
|
const ARMBaseInstrInfo &TII, unsigned MIFlags) {
|
2009-07-28 05:48:47 +00:00
|
|
|
bool isSub = NumBytes < 0;
|
|
|
|
if (isSub) NumBytes = -NumBytes;
|
|
|
|
|
|
|
|
// If profitable, use a movw or movt to materialize the offset.
|
|
|
|
// FIXME: Use the scavenger to grab a scratch register.
|
|
|
|
if (DestReg != ARM::SP && DestReg != BaseReg &&
|
|
|
|
NumBytes >= 4096 &&
|
|
|
|
ARM_AM::getT2SOImmVal(NumBytes) == -1) {
|
|
|
|
bool Fits = false;
|
|
|
|
if (NumBytes < 65536) {
|
|
|
|
// Use a movw to materialize the 16-bit constant.
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
|
|
|
|
.addImm(NumBytes)
|
2011-03-05 18:43:32 +00:00
|
|
|
.addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
|
2009-07-28 05:48:47 +00:00
|
|
|
Fits = true;
|
|
|
|
} else if ((NumBytes & 0xffff) == 0) {
|
|
|
|
// Use a movt to materialize the 32-bit constant.
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
|
|
|
|
.addReg(DestReg)
|
|
|
|
.addImm(NumBytes >> 16)
|
2011-03-05 18:43:32 +00:00
|
|
|
.addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
|
2009-07-28 05:48:47 +00:00
|
|
|
Fits = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Fits) {
|
|
|
|
if (isSub) {
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
|
|
|
|
.addReg(BaseReg, RegState::Kill)
|
|
|
|
.addReg(DestReg, RegState::Kill)
|
2011-03-05 18:43:32 +00:00
|
|
|
.addImm((unsigned)Pred).addReg(PredReg).addReg(0)
|
|
|
|
.setMIFlags(MIFlags);
|
2009-07-28 05:48:47 +00:00
|
|
|
} else {
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
|
|
|
|
.addReg(DestReg, RegState::Kill)
|
|
|
|
.addReg(BaseReg, RegState::Kill)
|
2011-03-05 18:43:32 +00:00
|
|
|
.addImm((unsigned)Pred).addReg(PredReg).addReg(0)
|
|
|
|
.setMIFlags(MIFlags);
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
while (NumBytes) {
|
|
|
|
unsigned ThisVal = NumBytes;
|
2009-08-07 00:34:42 +00:00
|
|
|
unsigned Opc = 0;
|
|
|
|
if (DestReg == ARM::SP && BaseReg != ARM::SP) {
|
|
|
|
// mov sp, rn. Note t2MOVr cannot be used.
|
2011-03-05 18:43:32 +00:00
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
|
|
|
|
.addReg(BaseReg).setMIFlags(MIFlags);
|
2009-08-07 00:34:42 +00:00
|
|
|
BaseReg = ARM::SP;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2010-03-08 22:56:15 +00:00
|
|
|
bool HasCCOut = true;
|
2009-08-07 00:34:42 +00:00
|
|
|
if (BaseReg == ARM::SP) {
|
|
|
|
// sub sp, sp, #imm7
|
|
|
|
if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
|
|
|
|
assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
|
|
|
|
Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
|
|
|
|
// FIXME: Fix Thumb1 immediate encoding.
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
|
2011-03-05 18:43:32 +00:00
|
|
|
.addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags);
|
2009-08-07 00:34:42 +00:00
|
|
|
NumBytes = 0;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// sub rd, sp, so_imm
|
|
|
|
Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
|
|
|
|
if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
|
|
|
|
NumBytes = 0;
|
|
|
|
} else {
|
|
|
|
// FIXME: Move this to ARMAddressingModes.h?
|
|
|
|
unsigned RotAmt = CountLeadingZeros_32(ThisVal);
|
|
|
|
ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
|
|
|
|
NumBytes &= ~ThisVal;
|
|
|
|
assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
|
|
|
|
"Bit extraction didn't work?");
|
|
|
|
}
|
2009-07-28 05:48:47 +00:00
|
|
|
} else {
|
2009-08-07 00:34:42 +00:00
|
|
|
assert(DestReg != ARM::SP && BaseReg != ARM::SP);
|
|
|
|
Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
|
|
|
|
if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
|
|
|
|
NumBytes = 0;
|
|
|
|
} else if (ThisVal < 4096) {
|
|
|
|
Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
|
2010-03-08 22:56:15 +00:00
|
|
|
HasCCOut = false;
|
2009-08-07 00:34:42 +00:00
|
|
|
NumBytes = 0;
|
|
|
|
} else {
|
|
|
|
// FIXME: Move this to ARMAddressingModes.h?
|
|
|
|
unsigned RotAmt = CountLeadingZeros_32(ThisVal);
|
|
|
|
ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
|
|
|
|
NumBytes &= ~ThisVal;
|
|
|
|
assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
|
|
|
|
"Bit extraction didn't work?");
|
|
|
|
}
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Build the new ADD / SUB.
|
2010-03-08 22:56:15 +00:00
|
|
|
MachineInstrBuilder MIB =
|
|
|
|
AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
|
|
|
|
.addReg(BaseReg, RegState::Kill)
|
2011-03-05 18:43:32 +00:00
|
|
|
.addImm(ThisVal)).setMIFlags(MIFlags);
|
2010-03-08 22:56:15 +00:00
|
|
|
if (HasCCOut)
|
|
|
|
AddDefaultCC(MIB);
|
2009-08-07 00:34:42 +00:00
|
|
|
|
2009-07-28 05:48:47 +00:00
|
|
|
BaseReg = DestReg;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
negativeOffsetOpcode(unsigned opcode)
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case ARM::t2LDRi12: return ARM::t2LDRi8;
|
|
|
|
case ARM::t2LDRHi12: return ARM::t2LDRHi8;
|
|
|
|
case ARM::t2LDRBi12: return ARM::t2LDRBi8;
|
|
|
|
case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
|
|
|
|
case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
|
|
|
|
case ARM::t2STRi12: return ARM::t2STRi8;
|
|
|
|
case ARM::t2STRBi12: return ARM::t2STRBi8;
|
|
|
|
case ARM::t2STRHi12: return ARM::t2STRHi8;
|
|
|
|
|
|
|
|
case ARM::t2LDRi8:
|
|
|
|
case ARM::t2LDRHi8:
|
|
|
|
case ARM::t2LDRBi8:
|
|
|
|
case ARM::t2LDRSHi8:
|
|
|
|
case ARM::t2LDRSBi8:
|
|
|
|
case ARM::t2STRi8:
|
|
|
|
case ARM::t2STRBi8:
|
|
|
|
case ARM::t2STRHi8:
|
|
|
|
return opcode;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
positiveOffsetOpcode(unsigned opcode)
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case ARM::t2LDRi8: return ARM::t2LDRi12;
|
|
|
|
case ARM::t2LDRHi8: return ARM::t2LDRHi12;
|
|
|
|
case ARM::t2LDRBi8: return ARM::t2LDRBi12;
|
|
|
|
case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
|
|
|
|
case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
|
|
|
|
case ARM::t2STRi8: return ARM::t2STRi12;
|
|
|
|
case ARM::t2STRBi8: return ARM::t2STRBi12;
|
|
|
|
case ARM::t2STRHi8: return ARM::t2STRHi12;
|
|
|
|
|
|
|
|
case ARM::t2LDRi12:
|
|
|
|
case ARM::t2LDRHi12:
|
|
|
|
case ARM::t2LDRBi12:
|
|
|
|
case ARM::t2LDRSHi12:
|
|
|
|
case ARM::t2LDRSBi12:
|
|
|
|
case ARM::t2STRi12:
|
|
|
|
case ARM::t2STRBi12:
|
|
|
|
case ARM::t2STRHi12:
|
|
|
|
return opcode;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
immediateOffsetOpcode(unsigned opcode)
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case ARM::t2LDRs: return ARM::t2LDRi12;
|
|
|
|
case ARM::t2LDRHs: return ARM::t2LDRHi12;
|
|
|
|
case ARM::t2LDRBs: return ARM::t2LDRBi12;
|
|
|
|
case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
|
|
|
|
case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
|
|
|
|
case ARM::t2STRs: return ARM::t2STRi12;
|
|
|
|
case ARM::t2STRBs: return ARM::t2STRBi12;
|
|
|
|
case ARM::t2STRHs: return ARM::t2STRHi12;
|
|
|
|
|
|
|
|
case ARM::t2LDRi12:
|
|
|
|
case ARM::t2LDRHi12:
|
|
|
|
case ARM::t2LDRBi12:
|
|
|
|
case ARM::t2LDRSHi12:
|
|
|
|
case ARM::t2LDRSBi12:
|
|
|
|
case ARM::t2STRi12:
|
|
|
|
case ARM::t2STRBi12:
|
|
|
|
case ARM::t2STRHi12:
|
|
|
|
case ARM::t2LDRi8:
|
|
|
|
case ARM::t2LDRHi8:
|
|
|
|
case ARM::t2LDRBi8:
|
|
|
|
case ARM::t2LDRSHi8:
|
|
|
|
case ARM::t2LDRSBi8:
|
|
|
|
case ARM::t2STRi8:
|
|
|
|
case ARM::t2STRBi8:
|
|
|
|
case ARM::t2STRHi8:
|
|
|
|
return opcode;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-08-27 01:23:50 +00:00
|
|
|
bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
|
|
|
|
unsigned FrameReg, int &Offset,
|
|
|
|
const ARMBaseInstrInfo &TII) {
|
2009-07-28 05:48:47 +00:00
|
|
|
unsigned Opcode = MI.getOpcode();
|
|
|
|
const TargetInstrDesc &Desc = MI.getDesc();
|
|
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
|
|
bool isSub = false;
|
|
|
|
|
|
|
|
// Memory operands in inline assembly always use AddrModeT2_i12.
|
|
|
|
if (Opcode == ARM::INLINEASM)
|
|
|
|
AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
|
2009-08-11 15:33:49 +00:00
|
|
|
|
2009-07-28 05:48:47 +00:00
|
|
|
if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
|
|
|
|
Offset += MI.getOperand(FrameRegIdx+1).getImm();
|
2009-08-07 00:34:42 +00:00
|
|
|
|
2010-01-19 21:08:28 +00:00
|
|
|
unsigned PredReg;
|
|
|
|
if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
|
2009-07-28 05:48:47 +00:00
|
|
|
// Turn it into a move.
|
2009-08-10 02:06:53 +00:00
|
|
|
MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
|
2009-07-28 05:48:47 +00:00
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
2010-01-19 21:08:28 +00:00
|
|
|
// Remove offset and remaining explicit predicate operands.
|
|
|
|
do MI.RemoveOperand(FrameRegIdx+1);
|
|
|
|
while (MI.getNumOperands() > FrameRegIdx+1 &&
|
|
|
|
(!MI.getOperand(FrameRegIdx+1).isReg() ||
|
|
|
|
!MI.getOperand(FrameRegIdx+1).isImm()));
|
2009-08-27 01:23:50 +00:00
|
|
|
return true;
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
|
|
|
|
2010-03-08 22:56:15 +00:00
|
|
|
bool isSP = FrameReg == ARM::SP;
|
|
|
|
bool HasCCOut = Opcode != ARM::t2ADDri12;
|
|
|
|
|
2009-07-28 05:48:47 +00:00
|
|
|
if (Offset < 0) {
|
|
|
|
Offset = -Offset;
|
|
|
|
isSub = true;
|
2009-08-07 00:34:42 +00:00
|
|
|
MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
|
|
|
|
} else {
|
|
|
|
MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Common case: small offset, fits into instruction.
|
|
|
|
if (ARM_AM::getT2SOImmVal(Offset) != -1) {
|
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
|
2010-03-08 22:56:15 +00:00
|
|
|
// Add cc_out operand if the original instruction did not have one.
|
|
|
|
if (!HasCCOut)
|
|
|
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
2009-08-27 01:23:50 +00:00
|
|
|
Offset = 0;
|
|
|
|
return true;
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
|
|
|
// Another common case: imm12.
|
2010-03-08 22:56:15 +00:00
|
|
|
if (Offset < 4096 &&
|
|
|
|
(!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
|
2009-08-07 00:34:42 +00:00
|
|
|
unsigned NewOpc = isSP
|
|
|
|
? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
|
|
|
|
: (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
|
|
|
|
MI.setDesc(TII.get(NewOpc));
|
2009-07-28 05:48:47 +00:00
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
|
2010-03-08 22:56:15 +00:00
|
|
|
// Remove the cc_out operand.
|
|
|
|
if (HasCCOut)
|
|
|
|
MI.RemoveOperand(MI.getNumOperands()-1);
|
2009-08-27 01:23:50 +00:00
|
|
|
Offset = 0;
|
|
|
|
return true;
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, extract 8 adjacent bits from the immediate into this
|
|
|
|
// t2ADDri/t2SUBri.
|
|
|
|
unsigned RotAmt = CountLeadingZeros_32(Offset);
|
|
|
|
unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
|
|
|
|
|
|
|
|
// We will handle these bits from offset, clear them.
|
|
|
|
Offset &= ~ThisImmVal;
|
|
|
|
|
|
|
|
assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
|
|
|
|
"Bit extraction didn't work?");
|
|
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
|
2010-03-08 22:56:15 +00:00
|
|
|
// Add cc_out operand if the original instruction did not have one.
|
|
|
|
if (!HasCCOut)
|
|
|
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
|
|
|
|
2009-07-28 05:48:47 +00:00
|
|
|
} else {
|
2009-09-15 17:56:18 +00:00
|
|
|
|
2010-02-06 00:24:38 +00:00
|
|
|
// AddrMode4 and AddrMode6 cannot handle any offset.
|
|
|
|
if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
|
2009-09-15 17:56:18 +00:00
|
|
|
return false;
|
|
|
|
|
2009-07-28 05:48:47 +00:00
|
|
|
// AddrModeT2_so cannot handle any offset. If there is no offset
|
|
|
|
// register then we change to an immediate version.
|
2009-08-07 00:34:42 +00:00
|
|
|
unsigned NewOpc = Opcode;
|
2009-07-28 05:48:47 +00:00
|
|
|
if (AddrMode == ARMII::AddrModeT2_so) {
|
|
|
|
unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
|
|
|
|
if (OffsetReg != 0) {
|
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
2009-08-27 01:23:50 +00:00
|
|
|
return Offset == 0;
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
2009-08-11 15:33:49 +00:00
|
|
|
|
2009-07-28 05:48:47 +00:00
|
|
|
MI.RemoveOperand(FrameRegIdx+1);
|
|
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
|
|
|
|
NewOpc = immediateOffsetOpcode(Opcode);
|
|
|
|
AddrMode = ARMII::AddrModeT2_i12;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned NumBits = 0;
|
|
|
|
unsigned Scale = 1;
|
|
|
|
if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
|
|
|
|
// i8 supports only negative, and i12 supports only positive, so
|
|
|
|
// based on Offset sign convert Opcode to the appropriate
|
|
|
|
// instruction
|
|
|
|
Offset += MI.getOperand(FrameRegIdx+1).getImm();
|
|
|
|
if (Offset < 0) {
|
|
|
|
NewOpc = negativeOffsetOpcode(Opcode);
|
|
|
|
NumBits = 8;
|
|
|
|
isSub = true;
|
|
|
|
Offset = -Offset;
|
|
|
|
} else {
|
|
|
|
NewOpc = positiveOffsetOpcode(Opcode);
|
|
|
|
NumBits = 12;
|
|
|
|
}
|
2010-02-06 00:24:38 +00:00
|
|
|
} else if (AddrMode == ARMII::AddrMode5) {
|
|
|
|
// VFP address mode.
|
|
|
|
const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
|
|
|
|
int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
|
|
|
|
if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
|
|
|
|
InstrOffs *= -1;
|
2009-07-28 05:48:47 +00:00
|
|
|
NumBits = 8;
|
|
|
|
Scale = 4;
|
|
|
|
Offset += InstrOffs * 4;
|
|
|
|
assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
|
|
|
|
if (Offset < 0) {
|
|
|
|
Offset = -Offset;
|
|
|
|
isSub = true;
|
|
|
|
}
|
2010-02-06 00:24:38 +00:00
|
|
|
} else {
|
|
|
|
llvm_unreachable("Unsupported addressing mode!");
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (NewOpc != Opcode)
|
|
|
|
MI.setDesc(TII.get(NewOpc));
|
|
|
|
|
|
|
|
MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
|
|
|
|
|
|
|
|
// Attempt to fold address computation
|
|
|
|
// Common case: small offset, fits into instruction.
|
|
|
|
int ImmedOffset = Offset / Scale;
|
|
|
|
unsigned Mask = (1 << NumBits) - 1;
|
|
|
|
if ((unsigned)Offset <= Mask * Scale) {
|
|
|
|
// Replace the FrameIndex with fp/sp
|
|
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
|
|
if (isSub) {
|
|
|
|
if (AddrMode == ARMII::AddrMode5)
|
|
|
|
// FIXME: Not consistent.
|
|
|
|
ImmedOffset |= 1 << NumBits;
|
2009-08-11 15:33:49 +00:00
|
|
|
else
|
2009-07-28 05:48:47 +00:00
|
|
|
ImmedOffset = -ImmedOffset;
|
|
|
|
}
|
|
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
2009-08-27 01:23:50 +00:00
|
|
|
Offset = 0;
|
|
|
|
return true;
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
2009-08-11 15:33:49 +00:00
|
|
|
|
2009-07-28 05:48:47 +00:00
|
|
|
// Otherwise, offset doesn't fit. Pull in what we can to simplify
|
2009-07-28 23:52:33 +00:00
|
|
|
ImmedOffset = ImmedOffset & Mask;
|
2009-07-28 05:48:47 +00:00
|
|
|
if (isSub) {
|
|
|
|
if (AddrMode == ARMII::AddrMode5)
|
|
|
|
// FIXME: Not consistent.
|
|
|
|
ImmedOffset |= 1 << NumBits;
|
2009-08-03 02:38:06 +00:00
|
|
|
else {
|
2009-07-28 05:48:47 +00:00
|
|
|
ImmedOffset = -ImmedOffset;
|
2009-08-03 02:38:06 +00:00
|
|
|
if (ImmedOffset == 0)
|
|
|
|
// Change the opcode back if the encoded offset is zero.
|
|
|
|
MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
|
|
|
|
}
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
|
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
|
|
Offset &= ~(Mask*Scale);
|
|
|
|
}
|
|
|
|
|
2009-08-27 01:23:50 +00:00
|
|
|
Offset = (isSub) ? -Offset : Offset;
|
|
|
|
return Offset == 0;
|
2009-07-28 05:48:47 +00:00
|
|
|
}
|
2010-06-09 19:26:01 +00:00
|
|
|
|
|
|
|
/// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
|
|
|
|
/// two-addrss instruction inserted by two-address pass.
|
|
|
|
void
|
|
|
|
Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
|
|
|
|
MachineInstr *UseMI,
|
|
|
|
const TargetRegisterInfo &TRI) const {
|
|
|
|
if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
|
|
|
|
SrcMI->getOperand(1).isKill())
|
|
|
|
return;
|
|
|
|
|
|
|
|
unsigned PredReg = 0;
|
|
|
|
ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
|
|
|
|
if (CC == ARMCC::AL || PredReg != ARM::CPSR)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Schedule the copy so it doesn't come between previous instructions
|
|
|
|
// and UseMI which can form an IT block.
|
|
|
|
unsigned SrcReg = SrcMI->getOperand(1).getReg();
|
|
|
|
ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
|
|
|
|
MachineBasicBlock *MBB = UseMI->getParent();
|
|
|
|
MachineBasicBlock::iterator MBBI = SrcMI;
|
|
|
|
unsigned NumInsts = 0;
|
|
|
|
while (--MBBI != MBB->begin()) {
|
|
|
|
if (MBBI->isDebugValue())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
MachineInstr *NMI = &*MBBI;
|
|
|
|
ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
|
|
|
|
if (!(NCC == CC || NCC == OCC) ||
|
|
|
|
NMI->modifiesRegister(SrcReg, &TRI) ||
|
|
|
|
NMI->definesRegister(ARM::CPSR))
|
|
|
|
break;
|
|
|
|
if (++NumInsts == 4)
|
|
|
|
// Too many in a row!
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (NumInsts) {
|
|
|
|
MBB->remove(SrcMI);
|
|
|
|
MBB->insert(++MBBI, SrcMI);
|
|
|
|
}
|
|
|
|
}
|
2010-06-22 01:18:16 +00:00
|
|
|
|
|
|
|
ARMCC::CondCodes
|
|
|
|
llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
|
|
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
|
|
|
|
return ARMCC::AL;
|
|
|
|
return llvm::getInstrPredicate(MI, PredReg);
|
|
|
|
}
|