2011-04-15 21:51:11 +00:00
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//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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//
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// Implements the info about Mips target spec.
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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#include "Mips.h"
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#include "MipsTargetMachine.h"
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#include "llvm/PassManager.h"
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2011-08-24 18:08:43 +00:00
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#include "llvm/Support/TargetRegistry.h"
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2007-06-06 07:42:06 +00:00
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using namespace llvm;
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2009-07-25 06:49:55 +00:00
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extern "C" void LLVMInitializeMipsTarget() {
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// Register the target.
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2011-09-21 03:00:58 +00:00
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RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
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2009-08-03 02:22:28 +00:00
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RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
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2011-09-21 03:00:58 +00:00
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RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target);
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RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget);
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2007-06-06 07:42:06 +00:00
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}
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// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
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2007-08-28 05:13:42 +00:00
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// The stack is always 8 byte aligned
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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2010-11-15 00:06:54 +00:00
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// offset from the stack/frame pointer, using StackGrowsUp enables
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2008-08-06 06:14:43 +00:00
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// an easier handling.
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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// Using CodeModel::Large enables different CALL behavior.
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2007-06-06 07:42:06 +00:00
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MipsTargetMachine::
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2011-07-19 06:37:02 +00:00
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MipsTargetMachine(const Target &T, StringRef TT,
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2011-12-02 22:16:29 +00:00
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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2011-07-20 07:51:56 +00:00
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Reloc::Model RM, CodeModel::Model CM,
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2011-11-16 08:38:26 +00:00
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CodeGenOpt::Level OL,
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2011-12-02 22:16:29 +00:00
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bool isLittle)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, isLittle),
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DataLayout(isLittle ?
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(Subtarget.isABI_N64() ?
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"e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
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"e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
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(Subtarget.isABI_N64() ?
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"E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
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"E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
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InstrInfo(*this),
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FrameLowering(Subtarget),
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TLInfo(*this), TSInfo(*this), JITInfo() {
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2007-10-09 03:01:19 +00:00
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}
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2007-06-06 07:42:06 +00:00
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2011-12-20 02:50:00 +00:00
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void MipsebTargetMachine::anchor() { }
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2011-09-21 03:00:58 +00:00
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MipsebTargetMachine::
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MipsebTargetMachine(const Target &T, StringRef TT,
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2011-12-02 22:16:29 +00:00
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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2011-11-16 08:38:26 +00:00
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Reloc::Model RM, CodeModel::Model CM,
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2011-12-02 22:16:29 +00:00
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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2011-09-21 03:00:58 +00:00
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2011-12-20 02:50:00 +00:00
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void MipselTargetMachine::anchor() { }
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2008-06-04 01:45:25 +00:00
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MipselTargetMachine::
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2011-07-19 06:37:02 +00:00
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MipselTargetMachine(const Target &T, StringRef TT,
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2011-12-02 22:16:29 +00:00
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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2011-11-16 08:38:26 +00:00
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Reloc::Model RM, CodeModel::Model CM,
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2011-12-02 22:16:29 +00:00
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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2008-06-04 01:45:25 +00:00
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2011-12-20 02:50:00 +00:00
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void Mips64ebTargetMachine::anchor() { }
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2011-09-21 03:00:58 +00:00
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Mips64ebTargetMachine::
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Mips64ebTargetMachine(const Target &T, StringRef TT,
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2011-12-02 22:16:29 +00:00
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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2011-11-16 08:38:26 +00:00
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Reloc::Model RM, CodeModel::Model CM,
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2011-12-02 22:16:29 +00:00
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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2011-09-21 03:00:58 +00:00
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2011-12-20 02:50:00 +00:00
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void Mips64elTargetMachine::anchor() { }
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2011-09-21 03:00:58 +00:00
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Mips64elTargetMachine::
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Mips64elTargetMachine(const Target &T, StringRef TT,
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2011-12-02 22:16:29 +00:00
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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2011-11-16 08:38:26 +00:00
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Reloc::Model RM, CodeModel::Model CM,
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2011-12-02 22:16:29 +00:00
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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2011-09-21 03:00:58 +00:00
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2010-11-15 00:06:54 +00:00
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// Install an instruction selector pass using
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2007-06-06 07:42:06 +00:00
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// the ISelDag to gen Mips code.
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bool MipsTargetMachine::
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2011-11-16 08:38:26 +00:00
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addInstSelector(PassManagerBase &PM)
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2010-01-20 06:34:14 +00:00
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{
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2007-06-06 07:42:06 +00:00
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PM.add(createMipsISelDag(*this));
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return false;
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}
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2010-11-15 00:06:54 +00:00
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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2007-06-06 07:42:06 +00:00
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// print out the code after the passes.
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bool MipsTargetMachine::
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addPreEmitPass(PassManagerBase &PM)
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2007-06-06 07:42:06 +00:00
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{
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2007-08-18 01:58:15 +00:00
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PM.add(createMipsDelaySlotFillerPass(*this));
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return true;
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2007-06-06 07:42:06 +00:00
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}
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2011-04-15 19:52:08 +00:00
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2011-05-04 17:54:27 +00:00
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bool MipsTargetMachine::
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2011-11-16 08:38:26 +00:00
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addPreRegAlloc(PassManagerBase &PM) {
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2011-09-27 16:58:43 +00:00
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// Do not restore $gp if target is Mips64.
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// In N32/64, $gp is a callee-saved register.
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if (!Subtarget.hasMips64())
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PM.add(createMipsEmitGPRestorePass(*this));
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2011-05-04 17:54:27 +00:00
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return true;
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}
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2011-04-15 19:52:08 +00:00
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bool MipsTargetMachine::
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addPostRegAlloc(PassManagerBase &PM) {
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2011-04-15 19:52:08 +00:00
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PM.add(createMipsExpandPseudoPass(*this));
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return true;
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}
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2011-07-21 16:28:51 +00:00
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bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
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2011-11-16 08:38:26 +00:00
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JITCodeEmitter &JCE) {
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2011-07-21 16:28:51 +00:00
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// Machine code emitter pass for Mips.
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PM.add(createMipsJITCodeEmitterPass(*this, JCE));
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return false;
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}
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