2010-02-21 21:54:14 +00:00
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//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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2011-07-25 19:33:48 +00:00
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#include "MCTargetDesc/X86BaseInfo.h"
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2011-07-25 18:43:53 +00:00
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#include "MCTargetDesc/X86FixupKinds.h"
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2012-03-17 18:46:09 +00:00
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#include "llvm/MC/MCAsmBackend.h"
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2010-03-19 09:28:12 +00:00
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#include "llvm/MC/MCAssembler.h"
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2010-12-17 16:59:53 +00:00
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#include "llvm/MC/MCELFObjectWriter.h"
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2010-05-06 20:34:01 +00:00
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#include "llvm/MC/MCExpr.h"
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2010-12-16 03:20:06 +00:00
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#include "llvm/MC/MCFixupKindInfo.h"
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2010-12-16 16:08:33 +00:00
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#include "llvm/MC/MCMachObjectWriter.h"
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2010-03-23 03:13:05 +00:00
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#include "llvm/MC/MCObjectWriter.h"
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2010-07-27 06:46:15 +00:00
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#include "llvm/MC/MCSectionCOFF.h"
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2010-03-19 09:29:03 +00:00
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#include "llvm/MC/MCSectionELF.h"
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2010-03-15 21:56:50 +00:00
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#include "llvm/MC/MCSectionMachO.h"
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2010-11-27 04:38:36 +00:00
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#include "llvm/Object/MachOFormat.h"
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2011-04-28 21:23:31 +00:00
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#include "llvm/Support/CommandLine.h"
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2010-10-22 15:52:49 +00:00
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#include "llvm/Support/ELF.h"
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2010-03-23 01:39:09 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2011-08-24 18:08:43 +00:00
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#include "llvm/Support/TargetRegistry.h"
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2010-03-23 01:39:09 +00:00
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#include "llvm/Support/raw_ostream.h"
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2010-02-21 21:54:14 +00:00
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using namespace llvm;
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2011-04-28 21:23:31 +00:00
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// Option to allow disabling arithmetic relaxation to workaround PR9807, which
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// is useful when running bitwise comparison experiments on Darwin. We should be
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// able to remove this once PR9807 is resolved.
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static cl::opt<bool>
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MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
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cl::desc("Disable relaxation of arithmetic instruction for X86"));
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2010-03-19 09:28:12 +00:00
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static unsigned getFixupKindLog2Size(unsigned Kind) {
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switch (Kind) {
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2012-02-05 05:38:58 +00:00
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default: llvm_unreachable("invalid fixup kind!");
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2010-11-28 14:17:56 +00:00
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case FK_PCRel_1:
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2011-12-24 14:47:52 +00:00
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case FK_SecRel_1:
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2010-03-19 09:28:12 +00:00
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case FK_Data_1: return 0;
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2010-11-28 14:17:56 +00:00
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case FK_PCRel_2:
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2011-12-24 14:47:52 +00:00
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case FK_SecRel_2:
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2010-03-19 09:28:12 +00:00
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case FK_Data_2: return 1;
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2010-11-28 14:17:56 +00:00
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case FK_PCRel_4:
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2010-03-19 09:28:12 +00:00
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case X86::reloc_riprel_4byte:
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case X86::reloc_riprel_4byte_movq_load:
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2010-09-30 03:11:42 +00:00
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case X86::reloc_signed_4byte:
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2010-10-24 17:35:42 +00:00
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case X86::reloc_global_offset_table:
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2011-12-24 14:47:52 +00:00
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case FK_SecRel_4:
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2010-03-19 09:28:12 +00:00
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case FK_Data_4: return 2;
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2010-12-27 00:36:05 +00:00
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case FK_PCRel_8:
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2011-12-24 14:47:52 +00:00
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case FK_SecRel_8:
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2010-03-19 09:28:12 +00:00
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case FK_Data_8: return 3;
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}
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}
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2010-07-07 22:27:31 +00:00
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namespace {
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2010-12-16 16:09:19 +00:00
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2010-12-17 17:45:22 +00:00
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class X86ELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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2011-12-21 17:00:36 +00:00
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X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
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bool HasRelocationAddend, bool foobar)
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: MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
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2010-12-17 17:45:22 +00:00
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};
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2011-07-25 23:24:55 +00:00
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class X86AsmBackend : public MCAsmBackend {
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2012-09-18 16:08:49 +00:00
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StringRef CPU;
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2010-02-21 21:54:14 +00:00
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public:
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2012-09-18 16:08:49 +00:00
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X86AsmBackend(const Target &T, StringRef _CPU)
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: MCAsmBackend(), CPU(_CPU) {}
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2010-03-19 09:28:12 +00:00
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2010-12-16 03:20:06 +00:00
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unsigned getNumFixupKinds() const {
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return X86::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
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{ "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
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{ "reloc_signed_4byte", 0, 4 * 8, 0},
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2011-12-24 14:47:52 +00:00
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{ "reloc_global_offset_table", 0, 4 * 8, 0}
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2010-12-16 03:20:06 +00:00
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};
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if (Kind < FirstTargetFixupKind)
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2011-07-25 23:24:55 +00:00
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return MCAsmBackend::getFixupKindInfo(Kind);
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2010-12-16 03:20:06 +00:00
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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2012-01-18 18:52:16 +00:00
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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2010-03-19 09:28:12 +00:00
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uint64_t Value) const {
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2010-05-26 15:18:31 +00:00
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unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
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2010-03-19 09:28:12 +00:00
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2010-12-06 19:08:48 +00:00
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assert(Fixup.getOffset() + Size <= DataSize &&
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2010-03-19 09:28:12 +00:00
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"Invalid fixup offset!");
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2011-08-04 00:38:45 +00:00
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2011-08-05 00:53:03 +00:00
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// Check that uppper bits are either all zeros or all ones.
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// Specifically ignore overflow/underflow as long as the leakage is
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// limited to the lower bits. This is to remain compatible with
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// other assemblers.
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2011-10-13 23:27:48 +00:00
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assert(isIntN(Size * 8 + 1, Value) &&
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2011-08-05 00:53:03 +00:00
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"Value does not fit in the Fixup field");
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2011-08-04 00:38:45 +00:00
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2010-03-19 09:28:12 +00:00
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for (unsigned i = 0; i != Size; ++i)
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2010-12-06 19:08:48 +00:00
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Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
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2010-03-19 09:28:12 +00:00
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}
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2010-03-23 01:39:09 +00:00
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2012-01-18 18:52:16 +00:00
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bool mayNeedRelaxation(const MCInst &Inst) const;
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2010-03-23 03:13:05 +00:00
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2011-12-06 00:47:03 +00:00
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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2013-01-08 00:22:56 +00:00
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const MCRelaxableFragment *DF,
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2011-12-06 00:47:03 +00:00
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const MCAsmLayout &Layout) const;
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2012-01-18 18:52:16 +00:00
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
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2010-03-23 02:36:58 +00:00
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2012-01-18 18:52:16 +00:00
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
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2010-02-21 21:54:14 +00:00
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};
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2010-10-10 22:04:20 +00:00
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} // end anonymous namespace
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2010-02-21 21:54:14 +00:00
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2010-10-26 14:09:12 +00:00
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static unsigned getRelaxedOpcodeBranch(unsigned Op) {
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2010-03-23 01:39:09 +00:00
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switch (Op) {
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default:
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return Op;
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case X86::JAE_1: return X86::JAE_4;
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case X86::JA_1: return X86::JA_4;
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case X86::JBE_1: return X86::JBE_4;
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case X86::JB_1: return X86::JB_4;
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case X86::JE_1: return X86::JE_4;
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case X86::JGE_1: return X86::JGE_4;
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case X86::JG_1: return X86::JG_4;
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case X86::JLE_1: return X86::JLE_4;
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case X86::JL_1: return X86::JL_4;
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case X86::JMP_1: return X86::JMP_4;
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case X86::JNE_1: return X86::JNE_4;
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case X86::JNO_1: return X86::JNO_4;
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case X86::JNP_1: return X86::JNP_4;
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case X86::JNS_1: return X86::JNS_4;
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case X86::JO_1: return X86::JO_4;
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case X86::JP_1: return X86::JP_4;
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case X86::JS_1: return X86::JS_4;
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}
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}
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2010-10-26 14:09:12 +00:00
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static unsigned getRelaxedOpcodeArith(unsigned Op) {
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switch (Op) {
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default:
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return Op;
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// IMUL
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case X86::IMUL16rri8: return X86::IMUL16rri;
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case X86::IMUL16rmi8: return X86::IMUL16rmi;
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case X86::IMUL32rri8: return X86::IMUL32rri;
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case X86::IMUL32rmi8: return X86::IMUL32rmi;
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case X86::IMUL64rri8: return X86::IMUL64rri32;
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case X86::IMUL64rmi8: return X86::IMUL64rmi32;
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// AND
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case X86::AND16ri8: return X86::AND16ri;
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case X86::AND16mi8: return X86::AND16mi;
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case X86::AND32ri8: return X86::AND32ri;
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case X86::AND32mi8: return X86::AND32mi;
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case X86::AND64ri8: return X86::AND64ri32;
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case X86::AND64mi8: return X86::AND64mi32;
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// OR
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case X86::OR16ri8: return X86::OR16ri;
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case X86::OR16mi8: return X86::OR16mi;
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case X86::OR32ri8: return X86::OR32ri;
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case X86::OR32mi8: return X86::OR32mi;
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case X86::OR64ri8: return X86::OR64ri32;
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case X86::OR64mi8: return X86::OR64mi32;
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// XOR
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case X86::XOR16ri8: return X86::XOR16ri;
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case X86::XOR16mi8: return X86::XOR16mi;
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case X86::XOR32ri8: return X86::XOR32ri;
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case X86::XOR32mi8: return X86::XOR32mi;
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case X86::XOR64ri8: return X86::XOR64ri32;
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case X86::XOR64mi8: return X86::XOR64mi32;
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// ADD
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case X86::ADD16ri8: return X86::ADD16ri;
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case X86::ADD16mi8: return X86::ADD16mi;
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case X86::ADD32ri8: return X86::ADD32ri;
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case X86::ADD32mi8: return X86::ADD32mi;
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case X86::ADD64ri8: return X86::ADD64ri32;
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case X86::ADD64mi8: return X86::ADD64mi32;
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// SUB
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case X86::SUB16ri8: return X86::SUB16ri;
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case X86::SUB16mi8: return X86::SUB16mi;
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case X86::SUB32ri8: return X86::SUB32ri;
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case X86::SUB32mi8: return X86::SUB32mi;
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case X86::SUB64ri8: return X86::SUB64ri32;
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case X86::SUB64mi8: return X86::SUB64mi32;
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// CMP
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case X86::CMP16ri8: return X86::CMP16ri;
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case X86::CMP16mi8: return X86::CMP16mi;
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case X86::CMP32ri8: return X86::CMP32ri;
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case X86::CMP32mi8: return X86::CMP32mi;
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case X86::CMP64ri8: return X86::CMP64ri32;
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case X86::CMP64mi8: return X86::CMP64mi32;
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2010-12-18 01:01:34 +00:00
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// PUSH
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case X86::PUSHi8: return X86::PUSHi32;
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2011-07-15 21:28:39 +00:00
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case X86::PUSHi16: return X86::PUSHi32;
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case X86::PUSH64i8: return X86::PUSH64i32;
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case X86::PUSH64i16: return X86::PUSH64i32;
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2010-10-26 14:09:12 +00:00
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}
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}
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static unsigned getRelaxedOpcode(unsigned Op) {
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unsigned R = getRelaxedOpcodeArith(Op);
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if (R != Op)
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return R;
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return getRelaxedOpcodeBranch(Op);
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}
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2012-01-18 18:52:16 +00:00
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bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
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2010-10-26 14:09:12 +00:00
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// Branches can always be relaxed.
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if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
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return true;
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2011-04-28 21:23:31 +00:00
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if (MCDisableArithRelaxation)
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return false;
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2010-05-26 17:45:29 +00:00
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// Check if this instruction is ever relaxable.
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2010-10-26 14:09:12 +00:00
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if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
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2010-05-26 17:45:29 +00:00
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return false;
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2010-05-26 15:18:31 +00:00
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2010-10-26 14:09:12 +00:00
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// Check if it has an expression and is not RIP relative.
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bool hasExp = false;
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bool hasRIP = false;
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for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
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const MCOperand &Op = Inst.getOperand(i);
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if (Op.isExpr())
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hasExp = true;
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if (Op.isReg() && Op.getReg() == X86::RIP)
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hasRIP = true;
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}
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// FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
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// how we do relaxations?
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return hasExp && !hasRIP;
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2010-03-23 03:13:05 +00:00
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}
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2011-12-06 00:47:03 +00:00
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bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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2013-01-08 00:22:56 +00:00
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const MCRelaxableFragment *DF,
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2011-12-06 00:47:03 +00:00
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const MCAsmLayout &Layout) const {
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// Relax if the value is too big for a (signed) i8.
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return int64_t(Value) != int64_t(int8_t(Value));
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}
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2010-03-23 01:39:09 +00:00
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// FIXME: Can tblgen help at all here to verify there aren't other instructions
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// we can relax?
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2012-01-18 18:52:16 +00:00
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void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
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2010-03-23 01:39:09 +00:00
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// The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
|
2010-05-26 18:15:06 +00:00
|
|
|
unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
|
2010-03-23 01:39:09 +00:00
|
|
|
|
2010-05-26 18:15:06 +00:00
|
|
|
if (RelaxedOp == Inst.getOpcode()) {
|
2010-03-23 01:39:09 +00:00
|
|
|
SmallString<256> Tmp;
|
|
|
|
raw_svector_ostream OS(Tmp);
|
2010-05-26 18:15:06 +00:00
|
|
|
Inst.dump_pretty(OS);
|
2010-05-26 15:18:13 +00:00
|
|
|
OS << "\n";
|
2010-04-07 22:58:41 +00:00
|
|
|
report_fatal_error("unexpected instruction to relax: " + OS.str());
|
2010-03-23 01:39:09 +00:00
|
|
|
}
|
|
|
|
|
2010-05-26 18:15:06 +00:00
|
|
|
Res = Inst;
|
2010-03-23 01:39:09 +00:00
|
|
|
Res.setOpcode(RelaxedOp);
|
|
|
|
}
|
|
|
|
|
2012-12-13 00:24:56 +00:00
|
|
|
/// \brief Write a sequence of optimal nops to the output, covering \p Count
|
|
|
|
/// bytes.
|
|
|
|
/// \return - true on success, false on failure
|
2012-01-18 18:52:16 +00:00
|
|
|
bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
|
2010-11-25 17:14:16 +00:00
|
|
|
static const uint8_t Nops[10][10] = {
|
2010-03-23 02:36:58 +00:00
|
|
|
// nop
|
|
|
|
{0x90},
|
|
|
|
// xchg %ax,%ax
|
|
|
|
{0x66, 0x90},
|
|
|
|
// nopl (%[re]ax)
|
|
|
|
{0x0f, 0x1f, 0x00},
|
|
|
|
// nopl 0(%[re]ax)
|
|
|
|
{0x0f, 0x1f, 0x40, 0x00},
|
|
|
|
// nopl 0(%[re]ax,%[re]ax,1)
|
|
|
|
{0x0f, 0x1f, 0x44, 0x00, 0x00},
|
|
|
|
// nopw 0(%[re]ax,%[re]ax,1)
|
|
|
|
{0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
|
|
|
|
// nopl 0L(%[re]ax)
|
|
|
|
{0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
|
|
|
|
// nopl 0L(%[re]ax,%[re]ax,1)
|
|
|
|
{0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
|
|
|
|
// nopw 0L(%[re]ax,%[re]ax,1)
|
|
|
|
{0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
|
|
|
|
// nopw %cs:0L(%[re]ax,%[re]ax,1)
|
|
|
|
{0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
|
|
|
|
};
|
|
|
|
|
2012-09-18 16:08:49 +00:00
|
|
|
// This CPU doesnt support long nops. If needed add more.
|
2012-10-13 17:28:35 +00:00
|
|
|
// FIXME: Can we get this from the subtarget somehow?
|
|
|
|
if (CPU == "generic" || CPU == "i386" || CPU == "i486" || CPU == "i586" ||
|
|
|
|
CPU == "pentium" || CPU == "pentium-mmx" || CPU == "geode") {
|
2012-09-18 16:08:49 +00:00
|
|
|
for (uint64_t i = 0; i < Count; ++i)
|
|
|
|
OW->Write8(0x90);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-03-05 00:02:23 +00:00
|
|
|
// 15 is the longest single nop instruction. Emit as many 15-byte nops as
|
|
|
|
// needed, then emit a nop of the remaining length.
|
|
|
|
do {
|
|
|
|
const uint8_t ThisNopLength = (uint8_t) std::min(Count, (uint64_t) 15);
|
|
|
|
const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
|
|
|
|
for (uint8_t i = 0; i < Prefixes; i++)
|
|
|
|
OW->Write8(0x66);
|
|
|
|
const uint8_t Rest = ThisNopLength - Prefixes;
|
|
|
|
for (uint8_t i = 0; i < Rest; i++)
|
|
|
|
OW->Write8(Nops[Rest - 1][i]);
|
|
|
|
Count -= ThisNopLength;
|
|
|
|
} while (Count != 0);
|
2010-03-23 02:36:58 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-03-23 01:39:09 +00:00
|
|
|
/* *** */
|
|
|
|
|
2010-07-07 22:27:31 +00:00
|
|
|
namespace {
|
2010-03-19 09:29:03 +00:00
|
|
|
class ELFX86AsmBackend : public X86AsmBackend {
|
|
|
|
public:
|
2011-12-21 17:00:36 +00:00
|
|
|
uint8_t OSABI;
|
2012-09-18 16:08:49 +00:00
|
|
|
ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU)
|
|
|
|
: X86AsmBackend(T, CPU), OSABI(_OSABI) {
|
2010-09-25 05:42:19 +00:00
|
|
|
HasReliableSymbolDifference = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
|
|
|
|
const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
|
2011-01-23 04:43:11 +00:00
|
|
|
return ES.getFlags() & ELF::SHF_MERGE;
|
2010-03-19 09:29:03 +00:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2010-05-21 11:39:07 +00:00
|
|
|
class ELFX86_32AsmBackend : public ELFX86AsmBackend {
|
|
|
|
public:
|
2012-09-18 16:08:49 +00:00
|
|
|
ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
|
|
|
|
: ELFX86AsmBackend(T, OSABI, CPU) {}
|
2010-08-16 18:36:14 +00:00
|
|
|
|
|
|
|
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
|
2012-10-30 17:33:39 +00:00
|
|
|
return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
|
2011-03-09 18:44:41 +00:00
|
|
|
}
|
2010-05-21 11:39:07 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
class ELFX86_64AsmBackend : public ELFX86AsmBackend {
|
|
|
|
public:
|
2012-09-18 16:08:49 +00:00
|
|
|
ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
|
|
|
|
: ELFX86AsmBackend(T, OSABI, CPU) {}
|
2010-08-16 18:36:14 +00:00
|
|
|
|
|
|
|
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
|
2012-10-30 17:33:39 +00:00
|
|
|
return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
|
2011-03-09 18:44:41 +00:00
|
|
|
}
|
2010-05-21 11:39:07 +00:00
|
|
|
};
|
|
|
|
|
2010-07-27 06:46:15 +00:00
|
|
|
class WindowsX86AsmBackend : public X86AsmBackend {
|
2010-08-21 05:58:13 +00:00
|
|
|
bool Is64Bit;
|
2010-10-16 18:23:53 +00:00
|
|
|
|
2010-07-27 06:46:15 +00:00
|
|
|
public:
|
2012-09-18 16:08:49 +00:00
|
|
|
WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
|
|
|
|
: X86AsmBackend(T, CPU)
|
2010-08-21 05:58:13 +00:00
|
|
|
, Is64Bit(is64Bit) {
|
2010-07-27 06:46:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
|
2011-12-24 02:14:02 +00:00
|
|
|
return createX86WinCOFFObjectWriter(OS, Is64Bit);
|
2010-07-27 06:46:15 +00:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2010-03-11 01:34:21 +00:00
|
|
|
class DarwinX86AsmBackend : public X86AsmBackend {
|
|
|
|
public:
|
2012-09-18 16:08:49 +00:00
|
|
|
DarwinX86AsmBackend(const Target &T, StringRef CPU)
|
|
|
|
: X86AsmBackend(T, CPU) { }
|
2010-03-11 01:34:21 +00:00
|
|
|
};
|
|
|
|
|
2010-03-15 21:56:50 +00:00
|
|
|
class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
|
|
|
|
public:
|
2012-09-18 16:08:49 +00:00
|
|
|
DarwinX86_32AsmBackend(const Target &T, StringRef CPU)
|
|
|
|
: DarwinX86AsmBackend(T, CPU) {}
|
2010-03-19 10:43:26 +00:00
|
|
|
|
|
|
|
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
|
2010-12-20 15:07:39 +00:00
|
|
|
return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
|
|
|
|
object::mach::CTM_i386,
|
|
|
|
object::mach::CSX86_ALL);
|
2010-03-19 10:43:26 +00:00
|
|
|
}
|
2010-03-15 21:56:50 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
|
|
|
|
public:
|
2012-09-18 16:08:49 +00:00
|
|
|
DarwinX86_64AsmBackend(const Target &T, StringRef CPU)
|
|
|
|
: DarwinX86AsmBackend(T, CPU) {
|
2010-03-18 00:58:53 +00:00
|
|
|
HasReliableSymbolDifference = true;
|
|
|
|
}
|
2010-03-15 21:56:50 +00:00
|
|
|
|
2010-03-19 10:43:26 +00:00
|
|
|
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
|
2010-12-20 15:07:39 +00:00
|
|
|
return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
|
|
|
|
object::mach::CTM_x86_64,
|
|
|
|
object::mach::CSX86_ALL);
|
2010-03-19 10:43:26 +00:00
|
|
|
}
|
|
|
|
|
2010-03-15 21:56:50 +00:00
|
|
|
virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
|
|
|
|
// Temporary labels in the string literals sections require symbols. The
|
|
|
|
// issue is that the x86_64 relocation format does not allow symbol +
|
|
|
|
// offset, and so the linker does not have enough information to resolve the
|
|
|
|
// access to the appropriate atom unless an external relocation is used. For
|
|
|
|
// non-cstring sections, we expect the compiler to use a non-temporary label
|
|
|
|
// for anything that could have an addend pointing outside the symbol.
|
|
|
|
//
|
|
|
|
// See <rdar://problem/4765733>.
|
|
|
|
const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
|
|
|
|
return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
|
|
|
|
}
|
2010-05-12 00:38:17 +00:00
|
|
|
|
|
|
|
virtual bool isSectionAtomizable(const MCSection &Section) const {
|
|
|
|
const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
|
|
|
|
// Fixed sized data sections are uniqued, they cannot be diced into atoms.
|
|
|
|
switch (SMO.getType()) {
|
|
|
|
default:
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case MCSectionMachO::S_4BYTE_LITERALS:
|
|
|
|
case MCSectionMachO::S_8BYTE_LITERALS:
|
|
|
|
case MCSectionMachO::S_16BYTE_LITERALS:
|
|
|
|
case MCSectionMachO::S_LITERAL_POINTERS:
|
|
|
|
case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
|
|
|
|
case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
|
|
|
|
case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
|
|
|
|
case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
|
|
|
|
case MCSectionMachO::S_INTERPOSING:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2010-03-15 21:56:50 +00:00
|
|
|
};
|
|
|
|
|
2010-10-10 22:04:20 +00:00
|
|
|
} // end anonymous namespace
|
2010-02-21 21:54:14 +00:00
|
|
|
|
2012-09-18 16:08:49 +00:00
|
|
|
MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, StringRef TT, StringRef CPU) {
|
2011-04-19 21:14:45 +00:00
|
|
|
Triple TheTriple(TT);
|
|
|
|
|
|
|
|
if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
|
2012-09-18 16:08:49 +00:00
|
|
|
return new DarwinX86_32AsmBackend(T, CPU);
|
2011-04-19 21:14:45 +00:00
|
|
|
|
2012-10-02 18:38:34 +00:00
|
|
|
if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
|
2012-09-18 16:08:49 +00:00
|
|
|
return new WindowsX86AsmBackend(T, false, CPU);
|
2011-04-19 21:14:45 +00:00
|
|
|
|
2011-12-21 17:00:36 +00:00
|
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
2012-09-18 16:08:49 +00:00
|
|
|
return new ELFX86_32AsmBackend(T, OSABI, CPU);
|
2010-02-21 21:54:14 +00:00
|
|
|
}
|
|
|
|
|
2012-09-18 16:08:49 +00:00
|
|
|
MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT, StringRef CPU) {
|
2011-04-19 21:14:45 +00:00
|
|
|
Triple TheTriple(TT);
|
|
|
|
|
|
|
|
if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
|
2012-09-18 16:08:49 +00:00
|
|
|
return new DarwinX86_64AsmBackend(T, CPU);
|
2011-04-19 21:14:45 +00:00
|
|
|
|
2012-10-02 18:38:34 +00:00
|
|
|
if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
|
2012-09-18 16:08:49 +00:00
|
|
|
return new WindowsX86AsmBackend(T, true, CPU);
|
2011-04-19 21:14:45 +00:00
|
|
|
|
2011-12-21 17:00:36 +00:00
|
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
2012-09-18 16:08:49 +00:00
|
|
|
return new ELFX86_64AsmBackend(T, OSABI, CPU);
|
2010-02-21 21:54:14 +00:00
|
|
|
}
|