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llvm-6502/test/MC/Disassembler/X86/simple-tests.txt

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specify a triple to use, fixing the test on non-x86-64 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91900 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 07:01:12 +00:00
# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
rewrite the file parser for the disassembler, implementing support for comments. Also, check in a simple testcase for the disassembler, including a test for r91864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 06:37:58 +00:00
# CHECK: int $33
0xCD 0x21
# CHECK: int $33
0xCD 0x21
# CHECK: addb %al, (%rax)
various cleanups, make the disassemble reject lines with too much data on them, for example: addb %al, (%rax) simple-tests.txt:11:5: error: excess data detected in input 0 0 0 0 0 ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91896 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 06:56:51 +00:00
0 0
rewrite the file parser for the disassembler, implementing support for comments. Also, check in a simple testcase for the disassembler, including a test for r91864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22 06:37:58 +00:00
# CHECK: callq -1234
0xe8 0x2e 0xfb 0xff 0xff
add some disassemble testcases for weird instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96045 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 23:46:48 +00:00
# CHECK: lfence
0x0f 0xae 0xe8
# CHECK: mfence
0x0f 0xae 0xf0
# CHECK: monitor
0x0f 0x01 0xc8
# CHECK: mwait
0x0f 0x01 0xc9
# CHECK: vmcall
0x0f 0x01 0xc1
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs fix swapgs to be spelled right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:41:14 +00:00
# CHECK: vmlaunch
0x0f 0x01 0xc2
# CHECK: vmresume
0x0f 0x01 0xc3
# CHECK: vmxoff
0x0f 0x01 0xc4
# CHECK: swapgs
add encoder support and tests for rdtscp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 03:42:24 +00:00
0x0f 0x01 0xf8
# CHECK: rdtscp
Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytes for the encoding and is not the same as vmptrld. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97992 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 22:17:26 +00:00
0x0f 0x01 0xf9
# CHECK: vmxon
0xf3 0x0f 0xc7 0x30
# CHECK: vmptrld
0x0f 0xc7 0x30
# CHECK: vmptrst
0x0f 0xc7 0x38
testcase for r101538, patch by Nico Schmidt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 17:22:06 +00:00
# CHECK: movl $0, -4(%rbp)
0xc7 0x45 0xfc 0x00 0x00 0x00 0x00
Eliminated the classification of control registers into %ecr_ and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
# CHECK: movq %cr0, %rcx
0x0f 0x20 0xc1
my work on adding segment registers to LEA missed the disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 04:23:55 +00:00
# CHECK: leal 4(%rsp), %ecx
Added a testcase for the ENTER instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05 00:21:40 +00:00
0x8d 0x4c 0x24 0x04
# CHECK: enter $1, $2
0xc8 0x01 0x00 0x02
Fixed handling of immediate operand sizes, which weren't properly reflecting the OperandSize attribute of the instruction leading to improper decoding of certain instructions with the 66H prefix. Also added a test case for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22 01:24:11 +00:00
# CHECK: movw $47416, -66(%rbp)
0x66 0xc7 0x45 0xbe 0x38 0xb9
Basic sanity checks to ensure that 2- and 3-byte VEX prefixes are working for triadic AVX instructions. This concludes the patch set to enable AVX support for the X86 disassebler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:32:46 +00:00
# CHECK: vaddpd %ymm13, %ymm1, %ymm0
0xc4 0xc1 0x75 0x58 0xc5
# CHECK: vaddps %ymm3, %ymm1, %ymm0
0xc5 0xf4 0x58 0xc3
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 05:28:50 +00:00
# CHECK: vandpd %ymm13, %ymm1, %ymm0
0xc4 0xc1 0x75 0x54 0xc5
# CHECK: vandps %ymm3, %ymm1, %ymm0
0xc5 0xf4 0x54 0xc3
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 06:57:46 +00:00
# CHECK: vzeroall
0xc5 0xfc 0x77
# CHECK: vcvtps2pd %xmm0, %ymm0
0xc5 0xfc 0x5a 0xc0
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 07:42:00 +00:00
# CHECK: vandps (%rdx), %xmm1, %xmm7
0xc5 0xf0 0x54 0x3a
Fix disassembling of VCVTSD2SI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 04:49:29 +00:00
# CHECK: vcvtss2sil %xmm0, %eax
0xc5 0xfa 0x2d 0xc0
# CHECK: vcvtsd2si %xmm0, %eax
0xc5 0xfb 0x2d 0xc0
# CHECK: vcvtsd2si %xmm0, %rax
0xc4 0xe1 0xfb 0x2d 0xc0
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 07:09:35 +00:00
# CHECK: vmaskmovpd %xmm0, %xmm1, (%rax)
0xc4 0xe2 0x71 0x2f 0x00
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 04:17:54 +00:00
# CHECK: vmovapd %xmm0, %xmm2
0xc5 0xf9 0x28 0xd0
Change X86 disassembly to print immediates values as signed by default. Special case those instructions that the immediate is not sign-extend. radr://8795217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 20:01:23 +00:00
# Check X86 immediates print as signed values by default. radr://8795217
# CHECK: andq $-16, %rsp
0x48 0x83 0xe4 0xf0
# Check these special case instructions that the immediate is not sign-extend.
# CHECK: blendps $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x0c 0xca 0x81
# CHECK: blendpd $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x0d 0xca 0x81
# CHECK: pblendw $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x0e 0xca 0x81
# CHECK: mpsadbw $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x42 0xca 0x81
# CHECK: dpps $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x40 0xca 0x81
# CHECK: dppd $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x41 0xca 0x81
# CHECK: insertps $129, %xmm2, %xmm1
0x66 0x0f 0x3a 0x21 0xca 0x81
# CHECK: vblendps $129, %ymm2, %ymm5, %ymm1
0xc4 0xe3 0x55 0x0c 0xca 0x81
# CHECK: vblendps $129, (%rax), %ymm5, %ymm1
0xc4 0xe3 0x55 0x0c 0x08 0x81
# CHECK: vblendpd $129, %ymm2, %ymm5, %ymm1
0xc4 0xe3 0x55 0x0d 0xca 0x81
# CHECK: vblendpd $129, (%rax), %ymm5, %ymm1
0xc4 0xe3 0x55 0x0d 0x08 0x81
# CHECK: vpblendw $129, %xmm2, %xmm5, %xmm1
0xc4 0xe3 0x51 0x0e 0xca 0x81
# CHECK: vmpsadbw $129, %xmm2, %xmm5, %xmm1
0xc4 0xe3 0x51 0x42 0xca 0x81
# CHECK: vdpps $129, %ymm2, %ymm5, %ymm1
0xc4 0xe3 0x55 0x40 0xca 0x81
# CHECK: vdpps $129, (%rax), %ymm5, %ymm1
0xc4 0xe3 0x55 0x40 0x08 0x81
# CHECK: vdppd $129, %xmm2, %xmm5, %xmm1
0xc4 0xe3 0x51 0x41 0xca 0x81
# CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1
0xc4 0xe3 0x69 0x21 0xcb 0x81
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