2004-02-25 21:02:21 +00:00
|
|
|
//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
|
2004-02-25 19:28:19 +00:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file was developed by the LLVM research group and is distributed under
|
|
|
|
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
2004-02-25 21:02:21 +00:00
|
|
|
// This file describes the SparcV8 instructions in TableGen format.
|
2004-02-25 19:28:19 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2004-02-25 21:02:21 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2004-02-26 00:37:12 +00:00
|
|
|
// Instruction format superclass
|
2004-02-25 21:02:21 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2004-02-25 19:28:19 +00:00
|
|
|
|
2004-02-25 21:02:21 +00:00
|
|
|
class InstV8 : Instruction { // SparcV8 instruction baseline
|
|
|
|
field bits<32> Inst;
|
|
|
|
|
|
|
|
let Namespace = "V8";
|
|
|
|
|
|
|
|
bits<2> op;
|
|
|
|
let Inst{31-30} = op; // Top two bits are the 'op' field
|
|
|
|
|
|
|
|
// Bit attributes specific to SparcV8 instructions
|
|
|
|
bit isPasi = 0; // Does this instruction affect an alternate addr space?
|
|
|
|
bit isPrivileged = 0; // Is this a privileged instruction?
|
|
|
|
}
|
2004-02-25 19:28:19 +00:00
|
|
|
|
2004-02-28 19:45:39 +00:00
|
|
|
include "SparcV8InstrInfo_F2.td"
|
|
|
|
include "SparcV8InstrInfo_F3.td"
|
2004-02-25 19:28:19 +00:00
|
|
|
|
2004-02-26 00:37:12 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Instructions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2004-02-28 19:37:18 +00:00
|
|
|
// Pseudo instructions.
|
|
|
|
def PHI : InstV8 {
|
|
|
|
let Name = "PHI";
|
|
|
|
}
|
|
|
|
def ADJCALLSTACKDOWN : InstV8 {
|
|
|
|
let Name = "ADJCALLSTACKDOWN";
|
|
|
|
}
|
|
|
|
def ADJCALLSTACKUP : InstV8 {
|
|
|
|
let Name = "ADJCALLSTACKUP";
|
|
|
|
}
|
|
|
|
|
2004-02-26 00:37:12 +00:00
|
|
|
// Section B.20: SAVE and RESTORE - p117
|
|
|
|
def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
|
|
|
|
def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
|
|
|
|
def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
|
|
|
|
def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
|
|
|
|
|
|
|
|
// Section B.24: Call and Link - p125
|
|
|
|
// This is the only Format 1 instruction
|
|
|
|
def CALL : InstV8 {
|
|
|
|
bits<30> disp;
|
|
|
|
|
|
|
|
let op = 1;
|
|
|
|
let Inst{29-0} = disp;
|
|
|
|
let Name = "call";
|
|
|
|
}
|
|
|
|
|
2004-03-04 00:56:25 +00:00
|
|
|
// Section B.9 - SETHI Instruction, p. 102
|
|
|
|
def SETHIi: F2_1<0b100, "sethi">;
|
|
|
|
|
2004-03-03 23:03:14 +00:00
|
|
|
// Section B.11 - Logical Instructions, p. 106
|
|
|
|
def ANDri : F3_2<2, 0b000001, "and">;
|
|
|
|
def ORrr : F3_1<2, 0b000010, "or">;
|
2004-03-04 00:56:25 +00:00
|
|
|
def ORri : F3_2<2, 0b000010, "or">;
|
2004-03-03 23:03:14 +00:00
|
|
|
|
|
|
|
// Section B.12 - Shift Instructions, p. 107
|
|
|
|
def SLLri : F3_1<2, 0b100101, "sll">;
|
|
|
|
def SRLri : F3_1<2, 0b100110, "srl">;
|
|
|
|
def SRAri : F3_1<2, 0b100111, "sra">;
|
|
|
|
|
|
|
|
// Section B.13 - Add Instructions, p. 108
|
|
|
|
def ADDrr : F3_1<2, 0b000000, "add">;
|
|
|
|
|
|
|
|
// Section B.25 - Jump and Link, p. 126
|
2004-02-26 00:37:12 +00:00
|
|
|
def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
|
|
|
|
def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
|
|
|
|
|