2007-06-06 07:42:06 +00:00
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//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Mips target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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2009-08-22 20:48:53 +00:00
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#include "MipsMCAsmInfo.h"
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2007-06-06 07:42:06 +00:00
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#include "MipsTargetMachine.h"
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#include "llvm/PassManager.h"
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2009-07-25 06:49:55 +00:00
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#include "llvm/Target/TargetRegistry.h"
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2007-06-06 07:42:06 +00:00
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using namespace llvm;
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2009-07-25 06:49:55 +00:00
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extern "C" void LLVMInitializeMipsTarget() {
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// Register the target.
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2009-08-03 02:22:28 +00:00
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RegisterTargetMachine<MipsTargetMachine> X(TheMipsTarget);
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RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
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2009-08-22 20:48:53 +00:00
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RegisterAsmInfo<MipsMCAsmInfo> A(TheMipsTarget);
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RegisterAsmInfo<MipsMCAsmInfo> B(TheMipselTarget);
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2007-06-06 07:42:06 +00:00
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}
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// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
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2007-08-28 05:13:42 +00:00
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// The stack is always 8 byte aligned
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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2008-08-06 06:14:43 +00:00
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// offset from the stack/frame pointer, using StackGrowsUp enables
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// an easier handling.
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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// Using CodeModel::Large enables different CALL behavior.
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2007-06-06 07:42:06 +00:00
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MipsTargetMachine::
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2009-08-03 02:22:28 +00:00
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MipsTargetMachine(const Target &T, const std::string &TT, const std::string &FS,
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2009-07-15 20:24:03 +00:00
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bool isLittle=false):
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2009-08-11 20:42:37 +00:00
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LLVMTargetMachine(T, TT),
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2009-08-03 02:22:28 +00:00
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Subtarget(TT, FS, isLittle),
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2009-11-07 19:07:32 +00:00
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DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-n32") :
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std::string("E-p:32:32:32-i8:8:32-i16:16:32-n32")),
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2008-06-04 01:45:25 +00:00
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InstrInfo(*this),
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FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0),
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2009-08-11 20:42:37 +00:00
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TLInfo(*this) {
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2008-07-14 14:42:54 +00:00
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// Abicall enables PIC by default
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2009-08-03 02:22:28 +00:00
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if (getRelocationModel() == Reloc::Default) {
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if (Subtarget.isABI_O32())
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setRelocationModel(Reloc::PIC_);
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else
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setRelocationModel(Reloc::Static);
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}
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2007-10-09 03:01:19 +00:00
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}
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2007-06-06 07:42:06 +00:00
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2008-06-04 01:45:25 +00:00
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MipselTargetMachine::
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2009-08-03 02:22:28 +00:00
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MipselTargetMachine(const Target &T, const std::string &TT,
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const std::string &FS) :
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MipsTargetMachine(T, TT, FS, true) {}
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2008-06-04 01:45:25 +00:00
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2007-06-06 07:42:06 +00:00
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsTargetMachine::
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2009-04-29 23:29:43 +00:00
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addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
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2007-06-06 07:42:06 +00:00
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{
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PM.add(createMipsISelDag(*this));
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return false;
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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bool MipsTargetMachine::
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2009-04-29 23:29:43 +00:00
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addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
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2007-06-06 07:42:06 +00:00
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{
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2007-08-18 01:58:15 +00:00
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PM.add(createMipsDelaySlotFillerPass(*this));
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return true;
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2007-06-06 07:42:06 +00:00
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}
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