llvm-6502/test/CodeGen/Hexagon/args.ll

; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s
; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7
; CHECK: r1:0 = combine(#2, #1)
; CHECK: r3:2 = combine(#4, #3)
; CHECK: r5:4 = combine(#6, #5)


define void @foo() nounwind {
entry:
  call void @bar(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)
  ret void
}

declare void @bar(i32, i32, i32, i32, i32, i32, i32)
Hexagon: Add encoding bits to the TFR64 instructions. Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8 2013-03-05 18:42:28 +00:00			`; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s \| FileCheck %s`
Use multiclass to define store instructions with base+immediate offset addressing mode and immediate stored value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169408 91177308-0d34-0410-b5e6-96231b3b80d8 2012-12-05 19:32:03 +00:00			`; CHECK: memw(r29{{ }}+{{ }}#0){{ }}={{ }}#7`
Hexagon: Pass to replace tranfer/copy instructions into combine instruction where possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8 2013-05-14 18:54:06 +00:00			`; CHECK: r1:0 = combine(#2, #1)`
			`; CHECK: r3:2 = combine(#4, #3)`
			`; CHECK: r5:4 = combine(#6, #5)`
Hexagon backend support git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146412 91177308-0d34-0410-b5e6-96231b3b80d8 2011-12-12 21:14:40 +00:00

			`define void @foo() nounwind {`
			`entry:`
			`call void @bar(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)`
			`ret void`
			`}`

			`declare void @bar(i32, i32, i32, i32, i32, i32, i32)`